Substrate structure including embedded semiconductor device and method of manufacturing the same
The present disclosure provides a substrate structure. The substrate structure includes an interconnection structure, a dielectric layer on the interconnection structure, an electronic component embedded in the dielectric layer, and a first conductive via penetrating through the dielectric layer and disposed adjacent to the electronic component. The interconnection structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The first conductive via and at least one of the first conductive layer and the second conductive layer define a first shielding structure surrounding the electronic component. A method of manufacturing a substrate structure is also disclosed.
1 . A substrate structure, comprising:
an interconnection structure;
a first dielectric layer adjacent to the interconnection structure;
a second dielectric layer disposed between the interconnection structure and the first dielectric layer;
a first electronic component in the first dielectric layer, wherein the first electronic component has an active surface facing away from the interconnection structure and a backside surface opposite to the active surface; and
a first conductive via penetrating through the first dielectric layer and electrically connected with the interconnection structure,
wherein the first conductive via exceeds past the backside surface of the first electronic component,
wherein the backside surface of the first electronic component and a surface of the first dielectric layer are substantially coplanar, and
wherein the backside surface of the first electronic component and the surface of the first dielectric layer directly contact the second dielectric layer.
2 . The substrate structure of claim 1 , wherein the interconnection structure includes a second conductive via tapers toward the first conductive via.
3 . The substrate structure of claim 2 , wherein the first conductive via and the second conductive via taper toward each other.
4 . The substrate structure of claim 3 , wherein the interconnection structure includes a conductive layer disposed between the first conductive via and the second conductive via.
5 . The substrate structure of claim 1 , wherein the first dielectric layer directly contacts the active surface of the first electronic component.
6 . The substrate structure of claim 1 , further comprising a second electronic component disposed adjacent to the interconnection structure and electrically connected with the interconnection structure.
7 . The substrate structure of claim 6 , further comprising an encapsulating layer disposed on the interconnection structure and encapsulating the second electronic component.
8 . The substrate structure of claim 1 , further comprising:
a conductive layer disposed on the first dielectric layer, wherein a line/space (L/S) of the conductive layer is narrower than an L/S of the interconnection structure; and
a second conductive via partially surrounded by the first dielectric layer and electrically connected with the conductive layer and the first electronic component.