IP Library Granted Patent US 12,469,816
Granted Patent B2
US 12,469,816 · App. 17/902,535 · Granted Nov 11, 2025

Semiconductor device

Inventor: Takeyuki Suzuki (Kaga Ishikawa, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H01L24/37H01L23/49562H01L24/32H01L24/83H01L24/84H01L2224/32014H01L2224/37005H01L2224/83801H01L2224/84359H01L2924/13055H01L2924/13091
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,469,816
App. No.
17/902,535
Granted
Nov 11, 2025
Kind
B2
Abstract

A semiconductor device includes: a first connector including a first plate having a first upper surface and a first terminal connected to the first plate, a first plate including a second plate and a third plate, a plate thickness of the second plate being thinner than a plate thickness of the third plate, the third plate being provided between the second plate and the first terminal; a semiconductor chip provided on the first upper surface; a first bonding material provided between the first upper surface and the semiconductor chip; a second connector provided on the semiconductor chip, a third connector, the first plate being provided between the first terminal and the third connector; a second bonding material provided between the second connector and the semiconductor chip; and a third bonding material provided between the second connector and the third connector.

Claims (58)

1 . A semiconductor device, comprising:

a first connector including a first plate having a first lower surface and a first upper surface and a first terminal connected to the first plate, the first plate including a second plate and a third plate, a plate thickness of the second plate being thinner than a plate thickness of the third plate, the third plate being provided between the second plate and the first terminal;

a semiconductor chip provided on the first upper surface, the semiconductor chip having a second lower surface facing the first upper surface, a first distance between the first lower surface of the second plate and the second lower surface being shorter than a second distance between the first lower surface of the third plate and the second lower surface;

a first bonding material provided between the first upper surface and the semiconductor chip;

a second connector provided on the semiconductor chip,

a third connector, the first plate being provided between the first terminal and the third connector;

a second bonding material provided between the second connector and the semiconductor chip; and

a third bonding material provided between the second connector and the third connector.

2 . The semiconductor device according to claim 1 , wherein the semiconductor chip has a convex shape on the side where the second connector is provided.

3 . The semiconductor device according to claim 1 ,

wherein the first upper surface has a slope on the first upper surface, and the slope is lowered from the third plate toward the second plate.

4 . The semiconductor device according to claim 3 ,

wherein an area of the slope when viewed from above is larger than an area of the semiconductor chip when viewed from above.

5 . The semiconductor device according to claim 3 ,

wherein an angle formed by the second upper surface of the slope and the first upper surface is preferably 0.2 degrees or more and 3 degrees or less.

6 . The semiconductor device according to claim 1 ,

wherein the second bonding material has a void.

7 . The semiconductor device according to claim 6 ,

wherein a diameter of the void is 1 mm or less.

8 . The semiconductor device according to claim 1 ,

wherein a third upper surface of the semiconductor chip has a first side and a second side facing the first side,

wherein, when viewed from above, the first side is provided between the second side and the third connector, and

wherein a thickness of the second bonding material in the vicinity of the first side is thinner than a thickness of the second bonding material in the vicinity of the second side.

9 . The semiconductor device according to claim 1 ,

wherein a third upper surface of the semiconductor chip has a first side and a second side facing the first side,

wherein, when viewed from above, the first side is provided between the second side and the third connector, and

wherein a thickness of the second bonding material in the vicinity of the first side is thicker than a thickness of the second bonding material in the vicinity of the second side.

10 . A semiconductor device, comprising:

a first connector including a first plate having a first upper surface and a first terminal connected to the first plate, the first plate including a second plate and a third plate, a plate thickness of the second plate being thinner than a plate thickness of the third plate, the third plate being provided between the second plate and the first terminal;

a semiconductor chip provided on the first upper surface;

a first bonding material provided between the first upper surface and the semiconductor chip;

a second connector provided on the semiconductor chip,

a third connector, the first plate being provided between the first terminal and the third connector;

a second bonding material provided between the second connector and the semiconductor chip; and

a third bonding material provided between the second connector and the third connector,

wherein the semiconductor chip has a convex shape on the side where the second connector is provided,

wherein the second bonding material has a void, and

wherein the void is located closer to an edge of the semiconductor chip than an apex of the convex shape.

11 . The semiconductor device according to claim 10 ,

wherein the first upper surface has a slope on the first upper surface, and the slope is lowered from the third plate toward the second plate.

12 . The semiconductor device according to claim 11 ,

wherein an area of the slope when viewed from above is larger than an area of the semiconductor chip when viewed from above.

13 . The semiconductor device according to claim 11 ,

wherein an angle formed by the second upper surface of the slope and the first upper surface is preferably 0.2 degrees or more and 3 degrees or less.

14 . The semiconductor device according to claim 10 ,

wherein a diameter of the void is 1 mm or less.

15 . The semiconductor device according to claim 10 ,

wherein a third upper surface of the semiconductor chip has a first side and a second side facing the first side,

wherein, when viewed from above, the first side is provided between the second side and the third connector, and

wherein a thickness of the second bonding material in the vicinity of the first side is thinner than a thickness of the second bonding material in the vicinity of the second side.

16 . The semiconductor device according to claim 10 ,

wherein a third upper surface of the semiconductor chip has a first side and a second side facing the first side,

wherein, when viewed from above, the first side is provided between the second side and the third connector, and

wherein a thickness of the second bonding material in the vicinity of the first side is thicker than a thickness of the second bonding material in the vicinity of the second side.

17 . The semiconductor device according to claim 10 ,

wherein the first plate has a first lower surface,

wherein the semiconductor chip has a second lower surface facing the first upper surface, and

wherein a first distance between the first lower surface of the second plate and the second lower surface is shorter than a second distance between the first lower surface of the third plate and the second lower surface.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 25, 2022
From: SUZUKI, TAKEYUKI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 061877/0686 →
Priority Claims (1)
JP 2022-045800 · Mar 22, 2022 · national
Continuity (1)
Related Publication 20230317672A1 · Oct 5, 2023
References Cited (31)
US 5866818A · Sumi · 1999 [cited by examiner]
US 7432594B2 · Ashida et al. · 2008 [cited by applicant]
US 10340347B1 · Yoshida et al. · 2019 [cited by applicant]
US 20040056362A1 · Moriguchi · 2004 [cited by examiner]
US 20040103530A1 · Adachi · 2004 [cited by examiner]
US 20050056927A1 · Teshima · 2005 [cited by examiner]
US 20060053909A1 · Shirasaka · 2006 [cited by examiner]
US 20070064429A1 · Mazzochette · 2007 [cited by examiner]
US 20070184584A1 · Shirasaka · 2007 [cited by examiner]
US 20070217476A1 · Yoshikawa · 2007 [cited by examiner]
US 20100075465A1 · Chew · 2010 [cited by examiner]
US 20120007236A1 · Bae · 2012 [cited by examiner]
US 20140015072A1 · Kang · 2014 [cited by examiner]
US 20150262917A1 · Fukui · 2015 [cited by applicant]
US 20160204047A1 · Sugiura et al. · 2016 [cited by applicant]
US 20160293804A1 · Haslbeck · 2016 [cited by examiner]
US 20190043788A1 · Iwai · 2019 [cited by examiner]
US 20190080979A1 · Tonedachi · 2019 [cited by examiner]
US 20200168575A1 · Bemmerl · 2020 [cited by examiner]
US 20210043816A1 · Bower · 2021 [cited by examiner]
US 20210225743A1 · Oogushi · 2021 [cited by examiner]
JP 2004111745A · 2004 [cited by applicant]
JP 4468115B2 · 2010 [cited by applicant]
JP 2012099559A · 2012 [cited by applicant]
JP 2015012065A · 2015 [cited by applicant]
JP 6447946B1 · 2019 [cited by applicant]
JP 2019087613A · 2019 [cited by applicant]
JP 2019186431A · 2019 [cited by applicant]
JP 2020184578A · 2020 [cited by applicant]
JP 2021034615A · 2021 [cited by applicant]
Notice of Reasons for Refusal (Office Action) mailed Apr. 1, 2025 in corresponding Japanese Patent Application No. 2022-045800 with English machine translation, 7 pages. [cited by applicant]