Methods and apparatus to identify a video decoding error
Methods, apparatus, systems and articles of manufacture to identify a video decoding error are disclosed. An example apparatus includes an atlas generator to generate atlas data for one or more atlases generated from input views of video; a hash generator to: perform a hash operation on the atlas data to generate a hash value; and include the hash value in a message; and a multiplexer to combine the one or more atlases, coded atlas data corresponding to the atlas data, and the message to generate a video bitstream.
1 . A video encoding apparatus comprising:
interface circuitry to obtain input views of video;
computer readable instructions; and
at least one processor circuit to be programmed by the computer readable instructions to at least:
generate mapping data that maps blocks in one or more atlases to patches, the one or more atlases generated from one or more of the input views of video;
perform a hash operation on the mapping data to generate a hash value;
include the hash value in a message; and
combine the one or more atlases and the message to generate a video bitstream.
2 . The apparatus of claim 1 , wherein one or more of the at least one processor circuit is to transmit the video bitstream to a decoding device.
3 . The apparatus of claim 1 , wherein the mapping data is a two-dimensional array.
4 . The apparatus of claim 1 , wherein the mapping data corresponds to a mapping of blocks to corresponding patches.
5 . The apparatus of claim 1 , wherein the one or more of the at least one processor circuit is to:
convert the input views of the video into at least one of a texture atlas or a depth atlas; and
encode the at least one of the texture atlas, the depth atlas, or the mapping data to generate encoded bitstream data.
6 . The apparatus of claim 1 , wherein one or more of the at least one processor circuit is to at least one of (i) generate the message or (ii) obtain the message from another device.
7 . The apparatus of claim 1 , wherein one or more of the at least one processor circuit is to hash the mapping data based on a 16 byte message digest algorithm 5 (MD5) sum.
8 . A non-transitory computer readable storage medium comprising instructions to cause at least one processor circuit to at least:
generate mapping data that maps block in one or more atlases to patches, the one or more atlases generated from one or more input views of video;
perform a hash operation on the mapping data to generate a hash value;
include the hash value in a message; and
combine the one or more atlases and the message to generate a video bitstream.
9 . The computer readable storage medium of claim 8 , wherein the instructions are to cause one or more of the at least one processor circuit to transmit the video bitstream to a decoding device.
10 . The computer readable storage medium of claim 8 , wherein the mapping data is a two-dimensional array.
11 . The computer readable storage medium of claim 8 , wherein the mapping data corresponds to a mapping of blocks in an atlas space to corresponding patches.
12 . The computer readable storage medium of claim 8 , wherein the instructions are to cause one or more of the at least one processor circuit to:
convert the input views of the video into at least one of a texture atlas or a depth atlas; and
encode the at least one of the texture atlas, the depth atlas, or the mapping data to generate encoded bitstream data.
13 . The computer readable storage medium of claim 8 , wherein the instructions are to cause one or more of the at least one processor circuit to at least one of (i) generate the message or (ii) obtain the message from another device.
14 . The computer readable storage medium of claim 8 , wherein the instructions are to cause one or more of the at least one processor circuit to hash the mapping data based on a 16 byte message digest algorithm 5 (MD5) sum.
15 . A video encoding method comprising:
generating, by at least one processor circuit programmed by at least one instruction, mapping data that maps blocks in one or more atlases to patches, the one or more atlases generated from one or more input views of video;
performing, by one or more of the at least one processor circuit, a hash operation on the mapping data to generate a hash value;
including the hash value in a message; and
combining the one or more atlases and the message to generate a video bitstream.
16 . The method of claim 15 , further including transmitting the video bitstream to a decoding device.
17 . The method of claim 15 , wherein the mapping data is a two-dimensional array corresponding to a map of the input views.
18 . The method of claim 15 , wherein the mapping data corresponds to a mapping of blocks to corresponding patches.
19 . The method of claim 15 , further including:
converting the input views of the video into at least one of a texture atlas or a depth atlas; and
encoding the at least one of the texture atlas, the depth atlas, or the mapping data to generate encoded bitstream data.
20 . The method of claim 15 , further including at least one of (i) generating the message or (ii) obtaining the message from another device.
21 . The method of claim 15 , further including hashing the mapping data based on a 16 byte message digest algorithm 5 (MD5) sum.
22 . A video decoding apparatus comprising:
interface circuitry to obtain input views of video;
computer readable instructions; and
at least one processor circuit to be programmed by the computer readable instructions to at least:
perform a hash operation on mapping data to determine a first hash value of the mapping data, the mapping data based on a volumetric video bitstream;
compare the first hash value to a second hash value of the mapping data, the second hash value included in the volumetric video bitstream; and
generate an error flag when the first hash value does not match the second hash value.
23 . The apparatus of claim 22 , wherein the one or more of the at least one processor circuit is to:
obtain the volumetric video bitstream; and
separate the mapping data and a message from the bitstream.
24 . The apparatus of claim 23 , wherein the message includes the second hash value.
25 . The apparatus of claim 22 , wherein the one or more of the at least one processor circuit is to generate the first hash value based on a same hash operation used to generate the second hash value.