Contact over active gate structures with uniform and conformal gate insulating cap layers for advanced integrated circuit structure fabrication
Contact over active gate (COAG) structures with uniform and conformal gate insulating cap layers, and methods of fabricating contact over active gate (COAG) structures using uniform and conformal gate insulating cap layers, are described. In an example, an integrated circuit structure includes a gate structure. An epitaxial source or drain structure is laterally spaced apart from the gate structure. A dielectric spacer is laterally between the gate structure and the epitaxial source or drain structure, the dielectric spacer having an uppermost surface below an uppermost surface of the gate structure. A gate insulating cap layer is on the uppermost surface of the gate structure and along upper portions of sides of the gate structure, the gate insulating cap layer distinct from the dielectric spacer.
1 . An integrated circuit structure, comprising:
a gate structure;
an epitaxial source or drain structure laterally spaced apart from the gate structure;
a dielectric spacer laterally between the gate structure and the epitaxial source or drain structure, the dielectric spacer having an uppermost surface below an uppermost surface of the gate structure; and
a gate insulating cap layer on the uppermost surface of the gate structure and along upper portions of sides of the gate structure, the gate insulating cap layer along an upper portion of a side of the dielectric spacer, and the gate insulating cap layer distinct from the dielectric spacer.
2 . The integrated circuit structure of claim 1 , wherein a portion of the gate insulating cap layer is vertically over a portion of the dielectric spacer.
3 . The integrated circuit structure of claim 2 , wherein the portion of the gate insulating cap layer is in contact with the portion of the dielectric spacer.
4 . The integrated circuit structure of claim 1 , wherein the gate insulating cap layer and the dielectric spacer comprise a same material.
5 . The integrated circuit structure of claim 1 , wherein the gate structure comprises a high-k gate dielectric layer, a workfunction layer, and a conductive fill material.
6 . An integrated circuit structure, comprising:
a conductive trench contact structure;
a gate structure laterally spaced apart from the conductive trench contact structure;
a dielectric spacer laterally between the conductive trench contact structure and the gate structure, the dielectric spacer having an uppermost surface below an uppermost surface of the conductive trench contact structure; and
a conductive trench contact insulating cap layer on the uppermost surface of the conductive trench contact structure and along upper portions of sides of the conductive trench contact structure, the conductive trench contact insulating cap layer along an upper portion of a side of the dielectric spacer, and the conductive trench contact insulating cap layer distinct from the dielectric spacer.
7 . The integrated circuit structure of claim 6 , wherein a portion of the conductive trench contact insulating cap layer is vertically over a portion of the dielectric spacer.
8 . The integrated circuit structure of claim 7 , wherein the portion of the conductive trench contact insulating cap layer is in contact with the portion of the dielectric spacer.
9 . The integrated circuit structure of claim 6 , wherein the conductive trench contact insulating cap layer and the dielectric spacer comprise a same material.
10 . The integrated circuit structure of claim 6 , wherein the gate structure comprises a high-k gate dielectric layer, a workfunction layer, and a conductive fill material.
11 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a gate structure;
an epitaxial source or drain structure laterally spaced apart from the gate structure;
a dielectric spacer laterally between the gate structure and the epitaxial source or drain structure, the dielectric spacer having an uppermost surface below an uppermost surface of the gate structure; and
a gate insulating cap layer on the uppermost surface of the gate structure and along upper portions of sides of the gate structure, the gate insulating cap layer along an upper portion of a side of the dielectric spacer, and the gate insulating cap layer distinct from the dielectric spacer.
12 . The computing device of claim 11 , further comprising:
a memory coupled to the board.
13 . The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
15 . The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
16 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a conductive trench contact structure;
a gate structure laterally spaced apart from the conductive trench contact structure;
a dielectric spacer laterally between the conductive trench contact structure and the gate structure, the dielectric spacer having an uppermost surface below an uppermost surface of the conductive trench contact structure; and
a conductive trench contact insulating cap layer on the uppermost surface of the conductive trench contact structure and along upper portions of sides of the conductive trench contact structure, the conductive trench contact insulating cap layer along an upper portion of a side of the dielectric spacer, and the conductive trench contact insulating cap layer distinct from the dielectric spacer.
17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.
18 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.
20 . The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.