Compute systems including a security processor
View Patent ↗A compute system includes a security processor, a component, a component memory, a first communication link, and a second communication link. The component memory stores machine readable instructions executable by the component. The first communication link communicatively couples the component memory to the security processor. The second communication link communicatively couples the component memory to the component. The security processor is to cryptographically authenticate the machine readable instructions stored in the component memory in a boot process.
1 . A compute system comprising:
a security processor;
a component;
a component memory storing machine readable instructions executable by the component;
a first communication link communicatively coupling the component memory to the security processor; and
a second communication link communicatively coupling the component memory to the component,
wherein the security processor is to;
send a signal to a reset pin of the component to disable the component; and
cryptographically authenticate, while the component is disabled, the machine readable instructions stored in the component memory in a boot process.
2 . The compute system of claim 1 , further comprising:
a security processor memory communicatively coupled to the security processor, the security processor memory storing machine readable instructions executable by the security processor, a private key, a secure certificate, and backup machine readable instructions for the component memory.
3 . The compute system of claim 1 , wherein the component comprises a reset input, and
wherein the security processor is to disable the component by applying a signal having a first state to the reset input of the component while the security processor is cryptographically authenticating the machine readable instructions stored in the component memory.
4 . The compute system of claim 1 , further comprising:
a switch electrically coupled between a power source and a power input of the component,
wherein the security processor is to control the switch to remove power from the component while the security processor is cryptographically authenticating the machine readable instructions stored in the component memory.
5 . The compute system of claim 1 , wherein the component comprises a Universal Serial Bus (USB) hub, a Local Area Network (LAN) controller, a Baseboard Management Controller (BMC), an Embedded Controller (EC), a Super Input/Output (SIO) controller, a high-speed switch controller, a signal conditioning controller, an external port controller, or a power delivery controller.
6 . The compute system of claim 1 , wherein each of the first communication link and the second communication link comprise a Serial Peripheral Interface (SPI) communication link, an enhanced Serial Peripheral Interface (eSPI) communication link, an Inter-Integrated Circuit (I2C) communication link, a SenseWire (I3C) communication link, or a System Management Bus (SMBus) communication link.
7 . The compute system of claim 1 , wherein the first communication link and the second communication link are electrically coupled to a single communication interface of the component memory.
8 . A compute system comprising:
a single security processor;
a plurality of components; and
a plurality of Read-Only Memories (ROMs), each ROM corresponding to a component of the plurality of components, each ROM storing machine readable instructions executable by the corresponding component, and each ROM communicatively coupled to the single security processor and the corresponding component;
wherein the single security processor is to, in a boot process, send a signal to a reset pin of each of the plurality of components to disable each of the plurality of components, cryptographically authenticate, while the plurality of components are disabled, the machine readable instructions stored in each of the ROMs with each of the plurality of components disabled, and enable each of the plurality of components with the machine readable instructions stored in each of the ROMs cryptographically authenticated.
9 . The compute system of claim 8 , wherein each of the plurality of ROMs comprises a Serial Peripheral Interface (SPI) ROM, an Electrically Erasable Programmable Read-Only Memory (EEPROM), or a flash memory.
10 . The compute system of claim 8 , wherein the single security processor is to cryptographically authenticate the machine readable instructions stored in each of the ROMs by asymmetric key exchange, certificate verification, and secure hash algorithm (SHA) checks between each of the ROMs and the single security processor.
11 . The compute system of claim 8 , wherein the single security processor is to erase a selected ROM of the plurality of ROMs and write backup machine readable instructions to the selected ROM in response to the cryptographic authentication of the selected ROM failing.
12 . A method to secure boot a plurality of components within a compute system, the method comprising:
sending a signal to a reset pin of each of the plurality of components;
disabling the plurality of components, each of the plurality of components communicatively coupled to a corresponding component memory of the compute system;
with each of the plurality of components disabled, cryptographically authenticating, via a security processor of the compute system, machine readable instructions stored in each corresponding component memory;
enabling each of the plurality of components with the machine readable instructions stored in each corresponding component memory cryptographically authenticated; and
with each of the plurality of components enabled, executing the machine readable instructions stored in each corresponding component memory via the corresponding component.
13 . The method of claim 12 , wherein disabling the plurality of components comprises applying a signal having a first state to a reset input of each of the plurality of components, and
wherein enabling each of the plurality of components comprises applying a signal having a second state to the reset input of each of the plurality of components.
14 . The method of claim 12 , wherein disabling the plurality of components comprises removing power from each of the plurality of components, and
wherein enabling each of the plurality of components comprises applying power to each of the plurality of components.
15 . The method of claim 12 , further comprising:
erasing a selected component memory in response to the machine readable instructions stored in the selected component memory failing the cryptographic authentication; and
writing backup machine readable instructions to the selected component memory.