Memory devices with a lower effective program verify level

1 . A memory device comprising:

an array of memory cells comprising a plurality of strings of series-connected memory cells;

a plurality of access lines, each access line of the plurality of access lines connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells; and

a controller configured to access the array of memory cells to program a selected memory cell of the array of memory cells to a first target level,

wherein the controller is further configured to:

apply a first voltage level to a first access line of the plurality of access lines connected to the selected memory cell;

apply a second voltage level higher than the first voltage level to a second access line of the plurality of access lines adjacent to the first access line;

apply a third voltage level between the first voltage level and the second voltage level to a third access line of the plurality of access lines adjacent to the first access line and connected to an erased memory cell; and

sense a first threshold voltage of the selected memory cell with the first voltage level applied to the first access line, the second voltage level applied to the second access line, and the third voltage level applied to the third access line.

2 . The memory device of claim 1 , wherein the controller is further configured to access the array of memory cells to program a further memory cell of the array of memory cells connected to the first access line to a second target level higher than the first target level; and

wherein the controller is further configured to:

apply a fourth voltage level higher than the first voltage level to the first access line;

apply the second voltage level to the second access line;

apply the second voltage level to the third access line; and

sense a second threshold voltage of the further memory cell.

3 . The memory device of claim 1 , wherein the controller is further configured to:

in response to the sensed first threshold voltage being less than a first program verify level, bias the selected memory cell for programming;

in response to the sensed first threshold voltage being greater than the first program verify level, inhibit programming of the selected memory cell; and

apply a particular program pulse to the selected memory cell.

4 . The memory device of claim 1 , wherein the third voltage level is selected such that capacitive coupling between the first access line and the third access line reduces the voltage level on the first access line from the first voltage level.

5 . The memory device of claim 1 , wherein the first voltage level is less than −1V, the second voltage level is greater than 6V, and the third voltage level is within a range between 1V and 5V.

6 . The memory device of claim 3 , wherein the controller is further configured to access the array of memory cells to program a further memory cell of the array of memory cells connected to the third access line to the first target level, and

wherein, with the sensed first threshold voltage greater than the first program verify level, the controller is further configured to:

apply the first voltage level to the third access line;

apply the second voltage level to the first access line;

apply the third voltage level to a fourth access line of the plurality of access lines adjacent to the third access line and connected to an erased memory cell; and

sense a second threshold voltage of the further memory cell.

7 . The memory device of claim 6 , wherein the controller is further configured to:

in response to the sensed second threshold voltage being less than the first program verify level, bias the further memory cell for programming;

in response to the sensed second threshold voltage being greater than the first program verify level, inhibit programming of the further memory cell; and

apply a subsequent program pulse to the further memory cell.

8 . The memory device of claim 7 , wherein, with the sensed second threshold voltage greater than the first program verify level, the controller is further configured to:

apply a fourth voltage level higher than the first voltage level to the first access line;

apply the second voltage level to the second access line;

apply the second voltage level to the third access line; and

sense a third threshold voltage of the selected memory cell.

9 . The memory device of claim 8 , wherein the controller is further configured to:

in response to the sensed third threshold voltage being less than a second program verify level higher than the first program verify level, bias the selected memory cell for programming;

in response to the sensed third threshold voltage being greater than the second program verify level, inhibit programming of the selected memory cell; and

apply a further subsequent program pulse to the selected memory cell.

10 . The memory device of claim 1 , wherein the memory cells comprise Quad-Level Cell (QLC) memory cells.

11 . A memory device comprising:

an array of memory cells comprising a plurality of strings of series-connected memory cells;

a plurality of access lines, each access line of the plurality of access lines connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells; and

a controller configured to program each respective memory cell connected to a selected first access line of the plurality of access lines to a respective target level,

wherein the controller is further configured to:

apply a first voltage level to the selected first access line;

apply a second voltage level higher than the first voltage level to a second access line of the plurality of access lines adjacent to the selected first access line;

apply a third voltage level between the first voltage level and the second voltage level to a third access line of the plurality of access lines adjacent to the selected first access line and connected to respective erased memory cells; and

sense a first threshold voltage of each respective memory cell connected to the selected first access line with the first voltage level applied to the selected first access line, the second voltage level applied to the second access line, and the third voltage level applied to the third access line.

12 . The memory device of claim 11 , wherein the controller is further configured to:

inhibit programming of each respective memory cell connected to the selected first access line in response to the sensed first threshold voltage of the respective memory cell being greater than a first program verify level for the respective memory cell;

enable programming of each respective memory cell connected to the selected first access line in response to the sensed first threshold voltage of the respective memory cell being less than the first program verify level for the respective memory cell; and

apply a particular program pulse to the selected first access line.

13 . The memory device of claim 12 , wherein the first program verify level for each respective memory cell comprises a coarse program verify level less than a fine program verify level for each respective memory cell.

14 . The memory device of claim 13 , wherein the controller is further configured to:

apply the second voltage level to the third access line;

sense a second threshold voltage of each respective memory cell connected to the selected access line;

inhibit programming of each respective memory cell connected to the selected first access line in response to the sensed second threshold voltage of the respective memory cell being greater than the fine program verify level for the respective memory cell;

enable programming of each respective memory cell connected to the selected first access line in response to the sensed second threshold voltage of the respective memory cell being less than the final program verify level for the respective memory cell; and

apply a subsequent program pulse to the selected first access line.

15 . The memory device of claim 11 , wherein the memory cells comprise Quad-Level Cell (QLC) memory cells.

16 . A method for programming an array of memory cells, the method comprising:

applying a first voltage level to a first access line connected to a selected memory cell of the array of memory cells to be programmed to a first target level;

applying a second voltage level higher than the first voltage level to a second access line adjacent to the first access line and connected to an unselected memory cell;

applying a third voltage level between the first voltage level and the second voltage level to a third access line adjacent to the first access line and connected to an erased memory cell; and

sensing a first threshold voltage of the selected memory cell with the first voltage level applied to the first access line, the second voltage level applied to the second access line, and the third voltage level applied to the third access line.

17 . The method of claim 16 , further comprising:

in response to the sensed first threshold voltage being less than a first program verify level, biasing the selected memory cell for programming;

in response to the sensed first threshold voltage being greater than the first program verify level, inhibiting programming of the selected memory cell; and

applying a particular program pulse to the selected memory cell.

18 . The method of claim 16 , further comprising:

applying a fourth voltage level higher than the first voltage level to the first access line;

applying the second voltage level to the second access line;

applying the second voltage level to the third access line; and

sensing a second threshold voltage of a further memory cell of the array of memory cells connected to the first access line to be programmed to a second target level higher than the first target level.

19 . The method of claim 18 , further comprising:

in response to the sensed second threshold voltage being less than a second program verify level higher than the first program verify level, biasing the further memory cell for programming;

in response to the sensed second threshold voltage being greater than the second program verify level, inhibiting programming of the further memory cell; and

applying a subsequent program pulse to the further memory cell.

20 . The method of claim 16 , wherein the memory cells comprise Quad-Level Cell (QLC) memory cells.