IP Library Granted Patent US 12,477,649
Granted Patent B2
US 12,477,649 · App. 18/351,251 · Granted Nov 18, 2025

Impedance tuning of microstrip traces

Inventors: Sandor Farkas (Round Rock, TX); Bhyrav Mutnury (Austin, TX)
Assignee: Dell Products L.P.
H05K1/0251H01P3/08H05K1/0298H05K1/115
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,477,649
App. No.
18/351,251
Granted
Nov 18, 2025
Kind
B2
Abstract

A printed circuit board comprising a first connection pad coupled to a first portion of a microstrip trace and a second connection pad coupled to a second portion of the microstrip trace. The microstrip trace has a first impedance along the first portion and a second impedance along the second portion. The printed circuit board also includes a conductive plane on a top surface of the microstrip trace, wherein the conductive plane includes a plurality of cutouts to reduce impedance mismatch between the first impedance and the second impedance.

Claims (32)

1 . A printed circuit board comprising:

a first connection pad coupled to a first portion of a microstrip trace;

a second connection pad coupled to a second portion of the microstrip trace;

the microstrip trace having a first impedance along the first portion and a second impedance along the second portion; and

a conductive plane on a top surface of the microstrip trace, wherein the conductive plane includes a plurality of cutouts to reduce impedance mismatch between the first impedance and the second impedance.

2 . The printed circuit board of claim 1 , wherein density of the cutouts is greater along the first portion than along the second portion.

3 . The printed circuit board of claim 1 , wherein the first impedance is greater than the second impedance.

4 . The printed circuit board of claim 1 , wherein a high-speed return current or a lower-speed return current can flow through the microstrip trace based on density of the cutouts.

5 . The printed circuit board of claim 1 , wherein a high-speed return current or a lower-speed return current can flow through the microstrip trace based on size of the cutouts.

6 . The printed circuit board of claim 1 , wherein the conductive plane is a conductive silk screen.

7 . The printed circuit board of claim 1 , wherein the microstrip trace has a varying impedance from the first portion to the second portion.

8 . The printed circuit board of claim 7 , wherein the varying impedance is highest at the first portion and lowest at the second portion.

9 . A microstrip trace, comprising:

a first portion having a first impedance;

a second portion having a second impedance; and

a conductive plane shielding the microstrip trace between the first portion and the second portion, wherein the conductive plane includes a plurality of cutouts to reduce impedance mismatch between the first impedance and the second impedance.

10 . The microstrip trace of claim 9 , wherein the first portion is physically coupled to a first connection pad.

11 . The microstrip trace of claim 9 , wherein the second portion is physically coupled to a second connection pad.

12 . The microstrip trace of claim 9 , wherein the conductive plane is a conductive silk screen.

13 . The microstrip trace of claim 9 , wherein the first impedance is not equal to the second impedance.

14 . The microstrip trace of claim 9 , wherein density of the cutouts is greater along the first portion than along the second portion.

15 . The microstrip trace of claim 9 , wherein impedance is greater along the first portion than along the second portion.

16 . An information handling system comprising:

a printed circuit board comprising:

a first connection pad coupled to a first portion of a microstrip trace;

a second connection pad coupled to a second portion of the microstrip trace;

the microstrip trace having a first impedance along the first portion and a second impedance along the second portion; and

a conductive plane that includes at least one cutout to reduce impedance mismatch between the first impedance and the second impedance.

17 . The information handling system of claim 16 , wherein the conductive plane is a conductive silk screen.

18 . The information handling system of claim 16 , wherein an impedance measurement is different around the first connection pad and the second connection pad.

19 . The information handling system of claim 16 , wherein the first connection pad is physically coupled with a first electronic component with an impedance requirement that is different than a second electronic component that is physically coupled to the second connection pad.

20 . The information handling system of claim 16 , wherein density of cutouts is different along the first connection pad than the second connection pad.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2023
From: FARKAS, SANDOR; MUTNURY, BHYRAV
To: DELL PRODUCTS L.P.
Reel/Frame 064231/0331 →
Continuity (1)
Related Publication 20250024589A1 · Jan 16, 2025
References Cited (8)
US 10255876B2 · Chang et al. · 2019 [cited by applicant]
US 20020084876A1 · Wright · 2002 [cited by examiner]
US 20050130501A1 · Timmins et al. · 2005 [cited by applicant]
US 20120274423A1 · Kato · 2012 [cited by examiner]
US 20130313013A1 · Porta · 2013 [cited by examiner]
US 20150327359A1 · Tuominen · 2015 [cited by examiner]
US 20180151151A1 · Chang et al. · 2018 [cited by applicant]
US 20200253036A1 · Chandra et al. · 2020 [cited by applicant]