IP Library Granted Patent US 12,484,249
Granted Patent B2
US 12,484,249 · App. 17/462,233 · Granted Nov 25, 2025

Gate structures in transistors and method of forming same

Inventors: Hsin-Yi Lee (Hsinchu, TW); Cheng-Lung Hung (Hsinchu, TW); Chi On Chui (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H10D30/6735H10D30/6757H10D62/118H10D64/01H10D64/691
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Quick Facts
Patent No.
US 12,484,249
App. No.
17/462,233
Granted
Nov 25, 2025
Kind
B2
Abstract

Embodiments include a device and method of forming a device, such as a nano-FET transistor, including a first nanostructure. A gate dielectric is formed around the first nanostructure. A gate electrode is formed over the gate dielectric, and the gate electrode includes a first work function metal. In the gate electrode, a first metal residue is formed at an interface between the gate dielectric and the first work function metal as a result of a treatment process performed prior to forming the first work function metal. The first metal residue has a metal element that is different than a metal element of the first work function metal.

Claims (38)

1 . A method comprising:

depositing a gate dielectric around a first nanostructure and a second nanostructure, the first nanostructure is disposed over the second nanostructure;

performing a fluorine treatment on the gate dielectric, wherein the fluorine treatment deposits a metallic residue on the gate dielectric, wherein the metallic residue is deposited by the fluorine treatment as discrete and disconnected pockets of metallic residue on the gate dielectric;

depositing a first p-type work function metal over the gate dielectric, the first p-type work function metal disposed around the first nanostructure and the second nanostructure; and

depositing a second p-type work function metal over the first p-type work function metal.

2 . The method of claim 1 , wherein the fluorine treatment comprises a deposition process that exposes a surface of the gate dielectric to one or more chemicals, wherein the one or more chemicals comprises a fluorine-containing precursor.

3 . The method of claim 2 , wherein the fluorine-containing precursor is WF x , NF x , TiF x , TaF x , or HfF x , wherein x is an integer in a range of 1 to 6.

4 . The method of claim 2 , wherein the fluorine treatment fails to trigger a reduction-oxidation reaction with the fluorine-containing precursor.

5 . The method of claim 1 , wherein the fluorine treatment is performed at a temperature in a range of 250° C. to 475° C.

6 . The method of claim 1 , wherein the fluorine treatment is performed for a duration of 1 second to 15 minutes.

7 . The method of claim 2 , wherein, other than the fluorine-containing precursor that forms discrete pockets of metallic residue on the gate dielectric, the fluorine-containing precursor remains unreacted prior to depositing the first p-type work function metal.

8 . A method comprising:

forming a stack of nanostructures over a substrate, the stack of nanostructures comprising a first nanostructure and a second nanostructure over the first nanostructure;

forming a first gate dielectric layer on the first nanostructure and the second nanostructure;

after forming the first gate dielectric layer, performing a fluorine treatment on the first gate dielectric layer, wherein the fluorine treatment comprises exposing the first gate dielectric layer to a first precursor, the first precursor including fluorine and a metal element, wherein all precursors of the fluorine treatment are the first precursor, wherein performing the fluorine treatment deposits a metal residue of the metal element on a surface of the first gate dielectric layer, wherein the metal residue of the metal element is deposited as discrete pockets of the metal element;

after performing the fluorine treatment, depositing one or more work function layers over the first gate dielectric layer and over the metal residue; and

forming a gate electrode fill layer over one or more work function layers.

9 . The method of claim 8 , wherein the first gate dielectric layer comprises hafnium oxide, wherein a ratio of the metal element of the metal residue to hafnium in the first gate dielectric layer in a region between the first nanostructure and the second nanostructure is less than 0.1.

10 . The method of claim 8 , wherein the metal element of the metal residue is tungsten.

11 . The method of claim 8 , wherein depositing one or more work function layers comprises:

forming a first work function layer over the first gate dielectric layer, wherein the metal element of the metal residue is different than metal elements of the first work function layer.

12 . The method of claim 11 , wherein depositing one or more work function layers comprises:

forming a second work function layer over the first work function layer, wherein the metal element of the metal residue is different than metal elements of the second work function layer.

13 . The method of claim 8 , wherein the first gate dielectric layer comprises hafnium oxide, and wherein a ratio of fluorine to hafnium in the first gate dielectric layer is in a range of 0.015 to 0.4.

14 . The method of claim 8 , wherein the one or more work function layers comprise at least one p-type work function layer.

15 . A method comprising:

forming a stack of nanostructures over a substrate, the stack of nanostructures comprising a first nanostructure and a second nanostructure over the first nanostructure;

forming a gate dielectric around the first nanostructure and the second nanostructure;

performing a fluorine treatment process that deposits discrete metal residues on the gate dielectric, wherein the fluorine treatment process does not deposit a continuous film on the gate dielectric, wherein after performing the fluorine treatment the gate dielectric is a metal oxide layer containing fluorine;

forming a first p-type work function metal over the gate dielectric, the first p-type work function metal disposed around the first nanostructure and the second nanostructure; and

depositing a second p-type work function metal over the first p-type work function metal.

16 . The method of claim 15 , wherein a ratio of fluorine to a metal of the metal oxide layer being in a range of between 0.015 and 0.40.

17 . The method of claim 15 , wherein the discrete metal residues comprise a tungsten residue, titanium residue, tantalum residue, or hafnium residue.

18 . The method of claim 15 , wherein forming the gate dielectric comprises:

forming a first dielectric layer; and

performing the fluorine treatment process using a deposition process that exposes a surface of the first dielectric layer to a fluorine-containing precursor.

19 . The method of claim 18 , wherein the fluorine-containing precursor is WF x , NF x , TiF x , TaF x , or HfF x , wherein x is an integer in a range of 1 to 6.

20 . The method of claim 15 , wherein the discrete metal residues comprise tungsten, titanium, tantalum, or hafnium.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2021
From: LEE, HSIN-YI; HUNG, CHENG-LUNG; CHUI, CHI ON
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 057338/0916 →
Continuity (1)
Related Publication 20230066477A1 · Mar 2, 2023
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