IP Library › Granted Patent US 12,487,820
Granted Patent B1
US 12,487,820 · App. 18/617,352 · Granted Dec 2, 2025

Apparatus and method for complex multiplication

Inventors: Robert Valentine (Kiryat Tivon, IL); Mark Charney (Lexington, MA); Raanan Sade (Portland, OR); Elmoustapha Ould-Ahmed-Vall (Chandler, AZ); Jesus Corbal (King City, OR); Roman S. Dubtsov (Novosibirsk, RU)
Assignee: Intel Corporation
G06F9/3001G06F7/4812G06F9/30014G06F9/30109G06F9/3013G06F9/3016G06F7/4806G06F9/30167G06F9/382G06F9/3824G06F17/10
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Quick Facts
Patent No.
US 12,487,820
App. No.
18/617,352
Granted
Dec 2, 2025
Kind
B1
Abstract

An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiplication of a first complex number and a second complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder, a first source register, and a second source register. The decoder is to decode an instruction to generate the decoded instruction. The first source register is to provide the first complex number and the second source register is to provide the second complex number.

Claims (36)

1 . A non-transitory machine-readable storage medium storing instructions that when executed by a machine are to cause the machine to perform operations, the operations including to:

receive a first instruction, the first instruction to specify a destination operand, a first source operand, and a second source operand; the first source operand to specify a first source register to store a first plurality of packed complex numbers, the second source operand is to specify a second source register to store a second plurality of packed complex numbers, and each of the first plurality and the second plurality of packed complex numbers is composed of a 16-bit half-precision floating-point element in an even position corresponding to a real component and a 16-bit half-precision floating-point element in an odd position corresponding to an imaginary component;

cause a processor to perform operations corresponding to the first instruction, including to, for at least one of the first plurality of packed complex numbers:

multiply an element in an even position and an element in an even position of a corresponding one of the second plurality of packed complex numbers to generate a first product,

multiply an element in an odd position and an element in an odd position of the corresponding one of the second plurality of packed complex numbers to generate a second product,

multiply the element in the odd position and the element in the even position of the corresponding one of the second plurality of packed complex numbers to generate a third product,

multiply the element in the even position and the element in the odd position of the corresponding one of the second plurality of packed complex numbers to generate a fourth product,

subtract the second product from the first product to generate a first result,

add the third product to the fourth product to generate a second result,

store the first result in an even position of a corresponding resulting packed complex number in a destination register, and

store the second result in an odd position of the corresponding resulting packed complex number in the destination register.

2 . The non-transitory machine-readable storage medium of claim 1 , wherein the operations corresponding to the first instruction also include copying the element in the even position of the corresponding one of the second plurality of packed complex numbers to an odd position of a transformed packed complex number.

3 . The non-transitory machine-readable storage medium of claim 1 , wherein the operations corresponding to the first instruction also include copying the element in the even position of the one of the first plurality of packed complex numbers to an odd position of a transformed packed complex number.

4 . The non-transitory machine-readable storage medium of claim 1 , wherein the operations corresponding to the first instruction also include copying the element in the odd position of the one of the second plurality of packed complex numbers to an even position of a transformed packed complex number.

5 . The non-transitory machine-readable storage medium of claim 1 , wherein the operations corresponding to the first instruction also include copying the element in the odd position of the corresponding one of the second plurality of packed complex numbers to an even position of a transformed packed complex number.

6 . The non-transitory machine-readable storage medium of claim 1 , wherein the operations also include:

receiving a second instruction; and

causing the processor to perform operations corresponding to the second instruction, including to, for at least an other one of the first plurality of packed complex numbers, add the second product to the first product to generate the first result, instead of subtracting the second product from the first product to generate the first result.

7 . A non-transitory machine-readable storage medium storing instructions that when executed by a machine are to cause the machine to perform operations, the operations including to:

convert a first instruction of a first instruction set into a first one or more instructions of a second, different instruction set, the first instruction to specify a destination operand, a first source operand, and a second source operand; the first source operand to specify a first source register to store a first plurality of packed complex numbers, the second source operand is to specify a second source register to store a second plurality of packed complex numbers, and each of the first plurality and the second plurality of packed complex numbers is composed of a 16-bit half-precision floating-point element in an even position corresponding to a real component and a 16-bit half-precision floating-point element in an odd position corresponding to an imaginary component;

cause a processor to execute the first one or more instructions of the second different instruction set to emulate the first instruction, including to, for at least one of the first plurality of packed complex numbers:

multiply an element in an even position and an element in an even position of a corresponding one of the second plurality of packed complex numbers to generate a first product,

multiply an element in an odd position and an element in an odd position of the corresponding one of the second plurality of packed complex numbers to generate a second product,

multiply the element in the odd position and the element in the even position of the corresponding one of the second plurality of packed complex numbers to generate a third product,

multiply the element in the even position and the element in the odd position of the corresponding one of the second plurality of packed complex numbers to generate a fourth product,

subtract the second product from the first product to generate a first result,

add the third product to the fourth product to generate a second result,

store the first result in an even position of a corresponding resulting packed complex number in a destination register, and

store the second result in an odd position of the corresponding resulting packed complex number in the destination register.

8 . The non-transitory machine-readable storage medium of claim 7 , wherein the operations corresponding to the first instruction also include copying the element in the even position of the corresponding one of the second plurality of packed complex numbers to an odd position of a transformed packed complex number.

9 . The non-transitory machine-readable storage medium of claim 7 , wherein the operations corresponding to the first instruction also include copying the element in the even position of the one of the first plurality of packed complex numbers to an odd position of a transformed packed complex number.

10 . The non-transitory machine-readable storage medium of claim 7 , wherein the operations corresponding to the first instruction also include copying the element in the odd position of the one of the second plurality of packed complex numbers to an even position of a transformed packed complex number.

11 . The non-transitory machine-readable storage medium of claim 7 , wherein the operations corresponding to the first instruction also include copying the element in the odd position of the corresponding one of the second plurality of packed complex numbers to an even position of a transformed packed complex number.

12 . The non-transitory machine-readable storage medium of claim 7 , wherein the operations also include:

converting a second instruction of the first instruction set into a second one or more instructions of the second, different instruction set; and

causing the processor to perform operations corresponding to the second instruction, including to, for at least an other one of the first plurality of packed complex numbers, add the second product to the first product to generate the first result, instead of subtracting the second product from the first product to generate the first result.

Continuity (3)
Continuation 17517351 · Nov 2, 2021
Continuation 16657007 · Oct 18, 2019
Continuation 15824333 · Nov 28, 2017
References Cited (43)
US 5179530A · Genusov et al. · 1993 [cited by applicant]
US 5793661A · Dulong et al. · 1998 [cited by applicant]
US 5862067A · Mennemeier et al. · 1999 [cited by applicant]
US 5983256A · Peleg et al. · 1999 [cited by applicant]
US 5996066A · Yung · 1999 [cited by applicant]
US 6307907B1 · Kim · 2001 [cited by applicant]
US 6651159B1 · Ramesh et al. · 2003 [cited by applicant]
US 7392368B2 · Khan et al. · 2008 [cited by applicant]
US 7424505B2 · Peleg et al. · 2008 [cited by applicant]
US 8271571B2 · Matsuyama et al. · 2012 [cited by applicant]
US 10452394B2 · Valentine et al. · 2019 [cited by applicant]
US 10489154B2 · Valentine et al. · 2019 [cited by applicant]
US 20030014457A1 · Desai et al. · 2003 [cited by applicant]
US 20050125635A1 · Symes et al. · 2005 [cited by applicant]
US 20090077154A1 · Matsuyama et al. · 2009 [cited by applicant]
US 20120173600A1 · Park et al. · 2012 [cited by applicant]
US 20130198254A1 · Peleg et al. · 2013 [cited by applicant]
US 20130283019A1 · Ould-Ahmed-Vall et al. · 2013 [cited by applicant]
US 20140052968A1 · Corbal et al. · 2014 [cited by applicant]
US 20160224340A1 · Moudgill et al. · 2016 [cited by applicant]
US 20170192780A1 · Valentine et al. · 2017 [cited by applicant]
US 20190310847A1 · Grocutt · 2019 [cited by applicant]
CN 1801082A · 2006 [cited by applicant]
CN 1890630A · 2007 [cited by applicant]
CN 104317774A · 2015 [cited by applicant]
CN 107102844A · 2017 [cited by applicant]
CN 108292223A · 2018 [cited by applicant]
CN 108885550A · 2018 [cited by applicant]
Non-Final Office Action, U.S. Appl. No. 15/824,333, Mar. 1, 2019, 33 pages. [cited by applicant]
Non-Final Office Action, U.S. Appl. No. 17/517,351, Jul. 24, 2023, 6 pages. [cited by applicant]
Non-Final Rejection Mailed on Jan. 27, 2021 for U.S. Appl. No. 16/657,007. [cited by applicant]
Notice of Allowance, U.S. Appl. No. 15/824,333, Jun. 28, 2019, 8 pages. [cited by applicant]
Notice of Allowance, U.S. Appl. No. 16/657,007, Jul. 22, 2021, 7 pages. [cited by applicant]
Notice of Allowance, U.S. Appl. No. 17/517,351, Dec. 28, 2023, 7 pages. [cited by applicant]
U.S. Appl. No. 15/824,324, Valentine et al. filed Nov. 28, 2017. [cited by applicant]
Beuchat et al., “Small Multiplier-based Multiplication and Division Operators for Virtex-II Devices”, Jul. 2002, 18 pages. [cited by applicant]
Chen et al., “Design of multiplier based on instruction set of ARMv4T architecture”, vol. 28, No. 2, Feb. 2011, 4 pages. [cited by applicant]
First Office Action, CN App. No. 201811258028.X, Oct. 19, 2024, 37 pages (19 pages of English Translation and 18 pages of Original Document. [cited by applicant]
Zhong et al., “A Vectorization of FIR Filter Supporting Arbitary Coefficients Length and Data Types”, vol. 41, No. 2, Feb. 2013, 6 pages. [cited by applicant]
“MMX”, Computer Applications, vol. 22, No. 11, Nov. 2002, 2 pages of Original Document Only. [cited by applicant]
First Office Action, CN App. No. 202210540570.4, Nov. 15, 2024, 11 pages (5 pages of English Translation and 6 pages of Original Document). [cited by applicant]
Jones et al., “Propagation of low-intensity Gaussian fields in photorefractive media with real and imaginary intensity-dependent refractive index components”, Appl Phys B (2011), 7 pages. [cited by applicant]
Office Action, CN App. No. 201811258028.X, Feb. 28, 2025, 27 pages (11 pages of English Translation of Search Report and 16 pages of Original Document). [cited by applicant]