Implementing burst transfers for predicated memory accesses in loop bodies for high-level synthesis
Implementing burst transfers for predicated accesses in high-level synthesis includes generating, using computer hardware, an intermediate representation of a design specified in a high-level programming language. The design is for an integrated circuit. Using the computer hardware, loop predicate information for one or more conditional statements within a loop body of the intermediate representation is determined. A plurality of memory accesses of the loop body guarded by the one or more conditional statements are determined to be sequential memory accesses based on the predicate information. The intermediate representation is modified by inserting one or more intrinsics therein indicating that the sequential memory accesses are to be implemented using a burst transfer mode of the integrated circuit.
1 . A method, comprising:
generating, using computer hardware, an intermediate representation of a design specified in a high-level programming language, wherein the design is for an integrated circuit;
using the computer hardware, determining loop predicate information for one or more conditional statements within a loop body of the intermediate representation;
determining, using the computer hardware, that a plurality of memory accesses of the loop body guarded by the one or more conditional statements are sequential memory accesses that execute in different iterations of the loop body based on the predicate information; and
modifying the intermediate representation by inserting one or more intrinsics therein indicating that the sequential memory accesses are to be implemented using a burst transfer mode of the integrated circuit.
2 . The method of claim 1 , further comprising:
detecting basic blocks within the intermediate representation.
3 . The method of claim 1 , further comprising:
generating a hardware description language version of the design from the intermediate representation, as modified, wherein the sequential memory accesses are designated for implementation in the integrated circuit using the burst transfer mode.
4 . The method of claim 1 , wherein the one or more conditional statements include a loop invariant predicate.
5 . The method of claim 1 , wherein the one or more conditional statements include a range predicate.
6 . The method of claim 1 , wherein the one or more conditional statements include a stride predicate.
7 . The method of claim 1 , further comprising:
generating sequential access chain information specifying a plurality of sequential memory accesses supported by selected predicate types, wherein the sequential access chain information includes a start access address, an access length, a list of the sequential memory accesses, and one or more predicates of the selected predicate types that guard the sequential memory accesses.
8 . A system, comprising:
one or more hardware processors configured to initiate operations including:
generating an intermediate representation of a design specified in a high-level programming language, wherein the design is for an integrated circuit;
determining loop predicate information for one or more conditional statements within a loop body of the intermediate representation;
determining that a plurality of memory accesses of the loop body guarded by the one or more conditional statements are sequential memory accesses that execute in different iterations of the loop body based on the predicate information; and
modifying the intermediate representation by inserting one or more intrinsics therein indicating that the sequential memory accesses are to be implemented using a burst transfer mode of the integrated circuit.
9 . The system of claim 8 , wherein the one or more processors are configured to initiate operations further comprising:
detecting basic blocks within the intermediate representation.
10 . The system of claim 8 , wherein the one or more processors are configured to initiate operations further comprising:
generating a hardware description language version of the design from the intermediate representation, as modified, wherein the sequential memory accesses are designated for implementation in the integrated circuit using the burst transfer mode.
11 . The system of claim 8 , wherein the one or more conditional statements include a loop invariant predicate.
12 . The system of claim 8 , wherein the one or more conditional statements include a range predicate.
13 . The system of claim 8 , wherein the one or more conditional statements include a stride predicate.
14 . The system of claim 8 , wherein the one or more processors are configured to initiate operations further comprising:
generating sequential access chain information specifying a plurality of sequential memory accesses supported by selected predicate types, wherein the sequential access chain information includes a start access address, an access length, a list of the sequential memory accesses, and one or more predicates of the selected predicate types that guard the sequential memory accesses.
15 . A computer program product comprising one or more computer readable storage mediums having program instructions embodied therewith, the program instructions executable by computer hardware to cause the computer hardware to initiate executable operations comprising:
generating an intermediate representation of a design specified in a high-level programming language, wherein the design is for an integrated circuit;
determining loop predicate information for one or more conditional statements within a loop body of the intermediate representation;
determining that a plurality of memory accesses of the loop body guarded by the one or more conditional statements are sequential memory accesses that execute in different iterations of the loop body based on the predicate information; and
modifying the intermediate representation by inserting one or more intrinsics therein indicating that the sequential memory accesses are to be implemented using a burst transfer mode of the integrated circuit.
16 . The computer program product of claim 15 , wherein the program instructions are executable by the computer hardware to initiate operations further comprising:
generating a hardware description language version of the design from the intermediate representation, as modified, wherein the sequential memory accesses are designated for implementation in the integrated circuit using the burst transfer mode.
17 . The computer program product of claim 15 , wherein the one or more conditional statements include a loop invariant predicate.
18 . The computer program product of claim 15 , wherein the one or more conditional statements include a range predicate.
19 . The computer program product of claim 15 , wherein the one or more conditional statements include a stride predicate.
20 . The computer program product of claim 15 , wherein the program instructions are executable by the computer hardware to initiate operations further comprising:
generating sequential access chain information specifying a plurality of sequential memory accesses supported by selected predicate types, wherein the sequential access chain information includes a start access address, an access length, a list of the sequential memory accesses, and one or more predicates of the selected predicate types that guard the sequential memory accesses.