IP Library Granted Patent US 12,488,409
Granted Patent B2
US 12,488,409 · App. 18/390,411 · Granted Dec 2, 2025

Graphics processing

Inventors: Daren Croxford (Swaffham Prior, GB); Mark Underwood (Cambridge, GB); Joseph Michael Richardson (Cambridge, GB)
Assignee: Arm Limited
G06T1/20G06F9/4881
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Quick Facts
Patent No.
US 12,488,409
App. No.
18/390,411
Granted
Dec 2, 2025
Kind
B2
Abstract

A graphics processor and method of operating a graphics processor to perform rendering followed by post-processing, in which post-processing tasks are permitted to be issued to processing cores of the graphics processor without waiting for all of the rendering tasks to have completed their processing, such that post-processing tasks are processed concurrently with rendering tasks.

Claims (38)

1 . A method of operating a graphics processor when performing graphics processing comprising a sequence of processing passes, the graphics processor including a set of one or more processing cores, the method comprising:

when performing a sequence of processing passes comprising a render pass and a post-processing pass, the render pass comprising a set of plural rendering tasks to be processed to generate an overall output for the render pass, and the post-processing pass comprising a set of plural post-processing tasks that use the overall output of the render pass:

issuing rendering tasks for the render pass to the one or more processing cores of the graphics processor for processing, the rendering tasks when executed generating respective sub-regions of the overall output for the render pass; and

issuing post-processing tasks to the one or more processing cores of the graphics processor for processing, the post-processing tasks when executed generating respective sub-regions of a post-processed output for the post-processing pass;

wherein the post-processing tasks are issued to the one more processing cores without waiting for processing for all of the rendering tasks for the render pass to have completed, such that post-processing tasks are interleaved with and processed concurrently with rendering tasks.

2 . The method of claim 1 , comprising

controlling an order of issuing rendering tasks based on dependencies of post-processing tasks upon rendering tasks.

3 . The method of claim 1 , comprising only issuing a post-processing task once the processing for the rendering task or tasks on which said post-processing task depends has or is likely to have completed.

4 . The method of claim 1 , comprising tracking the completion of rendering tasks, and controlling the order of issuing post-processing tasks based on the tracking of the completion of rendering tasks.

5 . The method of claim 1 , comprising storing regions of the overall render output generated by respective rendering tasks within local storage of the graphics processor, for use by post-processing tasks.

6 . The method of claim 1 , comprising issuing a post-processing task to the same processing core as one or more of the rendering tasks which said post-processing task depends on were issued to.

7 . The method of claim 1 , comprising issuing one or more post-processing tasks which require at least some data that is the same to the same processing core.

8 . The method of claim 1 , comprising issuing one or more combined tasks, each combined task comprising a rendering task and a post-processing task which are issued together to the same processing core.

9 . The method of claim 1 , wherein post-processing tasks for the post-processing pass comprise neural network processing tasks.

10 . A graphics processor comprising:

a set of one or more processing cores;

a task issuing circuit operable to control the issuing of tasks to the one or more processing cores for processing; and

wherein the task issuing circuit is configured to:

when the graphics processor is performing a sequence of processing passes comprising a render pass and a post-processing pass,

the render pass comprising a set of plural rendering tasks to be processed to generate an overall output for the render pass, the rendering tasks when executed generating respective sub-regions of the overall output for the render pass, and

the post-processing pass comprising a set of plural post-processing tasks that use the overall output of the render pass, the post-processing tasks when executed generating respective sub-regions of a post-processed output for the post-processing pass:

start issuing post-processing tasks without waiting for processing for all of the rendering tasks for the render pass to have completed, such that post-processing tasks are interleaved and can be processed concurrently with rendering tasks.

11 . The graphics processor of claim 10 , wherein the task issuing circuit is configured to at least one of:

control an order of issuing post-processing tasks based on dependencies of post-processing tasks upon rendering tasks; and

control an order of issuing rendering tasks based on dependencies of post-processing tasks upon rendering tasks.

12 . The graphics processor of claim 10 , wherein the task issuing circuit is configured to issue rendering tasks in a predetermined, static order.

13 . The graphics processor of claim 10 , wherein the task issuing circuit is configured to issue a post-processing task only once the processing for the rendering task or tasks on which it depends has or is likely to have completed.

14 . The graphics processor of claim 10 , wherein the task issuing circuit is configured to track the completion of rendering tasks, and control the order of issuing post-processing tasks based on the tracking of the completion of rendering tasks.

15 . The graphics processor of claim 10 , further configured to store regions of the overall render output generated by respective rendering tasks within local storage of the graphics processor, for use by post-processing tasks.

16 . The graphics processor of claim 10 , wherein the task issuing circuit is configured to issue a post-processing task to the same processing core as one or more of the rendering tasks which said post-processing task depends on were issued to.

17 . The graphics processor of claim 10 , wherein the task issuing circuit is configured to issue one or more post-processing tasks which require at least some data that is the same to the same processing core.

18 . The graphics processor of claim 10 , wherein the task issuing circuit is configured to issue one or more combined tasks, each combined task comprising a rendering task and a post-processing task which are issued together to the same processing core.

19 . The graphics processor of claim 10 , wherein the post-processing tasks for the post-processing pass comprise neural network processing tasks.

20 . A non-transitory computer readable storage medium storing computer software code which when executing on at least one processor performs a method of operating a graphics processor when performing graphics processing comprising a sequence of processing passes, the graphics processor including a set of one or more processing cores, the method comprising:

when performing a sequence of processing passes comprising a render pass and a post-processing pass, the render pass comprising a set of plural rendering tasks to be processed to generate an overall output for the render pass, and the post-processing pass comprising a set of plural post-processing tasks that use the overall output of the render pass:

issuing rendering tasks for the render pass to the one or more processing cores of the graphics processor for processing, the rendering tasks when executed generating respective sub-regions of the overall output for the render pass; and

issuing post-processing tasks to the one or more processing cores of the graphics processor for processing, the post-processing tasks when executed generating respective sub-regions of a post-processed output for the post-processing pass;

wherein the post-processing tasks are issued to the one more processing cores without waiting for processing for all of the rendering tasks for the render pass to have completed, such that post-processing tasks are interleaved with and processed concurrently with rendering tasks.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2024
From: CROXFORD, DAREN; UNDERWOOD, MARK; RICHARDSON, JOSEPH MICHAEL
To: ARM LIMITED
Reel/Frame 066204/0792 →
Continuity (1)
Related Publication 20250209562A1 · Jun 26, 2025
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