Monotonic counter implemented in non-volatile resistive switching memory
A monotonic counter implemented at least in part in non-volatile memory hardware is described herein. Compared with software counting algorithms, the disclosed embodiments significantly enhance security of disclosed monotonic counters. In some aspects of the disclosed embodiments, a non-binary coded decimal (BCD) counting algorithm can be utilized in whole or in part to enhance longevity of non-volatile memory cells storing monotonic counter values. Various aspects of the present specification disclose both a monotonic increase counter, and a monotonic decrease counter.
1 . A method for counting in non-volatile resistive switching memory, comprising:
initiating a count algorithm;
initializing a number, M, of non-volatile memory (NVM) cells for storing a portion of a variable count and characterizing one cell of the NVM cells as a primary bit (PB) and another cell of the NVM cells as a final bit (FB);
detecting occurrence of an event associated with the count algorithm;
incrementing an interval counter in response to detecting occurrence of the event;
detecting an I th occurrence of the event, wherein I is an integer specified by the count algorithm to be greater than one;
changing a state of the PB of the NVM cells from an original state to a changed state and resetting the interval counter in response to detecting the I th occurrence of the event;
detecting a second I th occurrence of the event and resetting the interval counter;
changing a second bit of the NVM cells to the changed state and resetting the interval counter;
detecting an M th instance of I th occurrences of the event and resetting the interval counter, where M is equal to the number of NVM cells;
changing the FB of the NVM cells to the changed state; and
reading a value of the variable count at least in part by adding a number, Y, of NVM cells matching a read state of the PB.
2 . The method of claim 1 , wherein reading the value of the variable count further comprises:
determining a current state of the PB;
reading states of the NVM cells;
determining the number, Y, of NVM cells, including the PB, having the same state as the PB; and
multiplying the integer I by the number Y.
3 . The method of claim 2 , further comprising:
incrementing a base multiplier value of a base multiplier number in response to changing the FB of the NVM cells to the changed state;
detecting an M+1 th instance of I th occurrences of the event; and
changing the PB of the NVM cells from the changed state to the original state and resetting the interval counter.
4 . The method of claim 3 , wherein reading the value of the variable counter further comprises:
multiplying the number, M, of NVM cells by the base multiplier value to generate a cycle count;
adding the number Y to the cycle count to generate a sum of the cycle count and Y; and
multiplying the integer I by the sum of the cycle count and Y.
5 . The method of claim 3 , further comprising:
detecting an M+2th instance of I th occurrences of the event; and
changing the second bit of the NVM cells to the original state and resetting the interval counter.
6 . The method of claim 5 , further comprising:
detecting a 2*M th instance of I th occurrences of the event;
changing the FB of the NVM cells from the changed state to the original state and resetting the interval counter; and
further incrementing the base multiplier value of the base multiplier number in response to changing the FB of the NVM cells to the original state from the changed state.
7 . The method of claim 3 , wherein the base multiplier value is stored in a set of NVM cells separate from the number, M, of NVM cells.
8 . The method of claim 1 , wherein incrementing the interval counter further comprises incrementing a current interval value stored in volatile memory in response to detecting occurrence of the event and resetting the interval value further comprises setting the current interval value to zero.
9 . The method of claim 8 , wherein the integer I is a fixed value stored in non-volatile memory.