Stacked field effect transistor
A semiconductor device is provided. The semiconductor device includes a bottom field effect transistor (FET) including a bottom source-drain epitaxial layer formed on sides of the bottom FET; a top FET stacked over the bottom FET; a back-end-of-line (BEOL) layer formed on the top FET; a bottom gate contact formed in contact with the bottom FET and having an extending portion of the bottom gate contact that extends laterally over the bottom source-drain epitaxial layer; and a top gate contact formed in contact with the extending portion of the bottom gate contact and electrically connecting the bottom gate contact to the BEOL layer.
1 . A semiconductor device comprising:
a bottom field effect transistor (FET) including a bottom source-drain epitaxial layer formed on sides of the bottom FET;
a top FET stacked over the bottom FET;
a back-end-of-line (BEOL) layer formed on the top FET;
a bottom gate contact formed in contact with the bottom FET and having an extending portion of the bottom gate contact that extends laterally over the bottom source-drain epitaxial layer; and
a top gate contact formed in contact with the extending portion of the bottom gate contact and electrically connecting the bottom gate contact to the BEOL layer.
2 . The semiconductor device according to claim 1 , wherein the bottom FET includes alternating layers of active semiconductor layers and high-κ metal gate layers.
3 . The semiconductor device according to claim 2 , further comprising a gate spacer surrounding the high-κ metal gate layers.
4 . The semiconductor device according to claim 1 , further comprising a late gate cut insulating layer extending from the top FET to the bottom FET.
5 . The semiconductor device according to claim 4 , wherein the late gate cut insulating layer electrically isolates the top FET and the bottom FET.
6 . The semiconductor device according to claim 1 , wherein the bottom gate contact is formed of a high-κ material.
7 . The semiconductor device according to claim 1 , wherein the top gate contact is laterally offset from the top FET and the bottom FET.
8 . The semiconductor device according to claim 1 , further comprising a first bonding oxide layer formed at a same level as the bottom gate contact.
9 . The semiconductor device according to claim 1 , wherein an active region of the top FET is smaller than an active region of the bottom FET.
10 . The semiconductor device according to claim 1 , wherein an active region of the top FET is laterally offset from an active region of the bottom FET.
11 . A method of manufacturing a semiconductor device, the method comprising:
forming a bottom field effect transistor (FET) including a bottom source-drain epitaxial layer on sides of the bottom FET;
forming a top FET stacked over the bottom FET;
forming a back-end-of-line (BEOL) layer on the top FET;
forming a bottom gate contact in contact with the bottom FET and having an extending portion of the bottom gate contact that extends laterally over the bottom source-drain epitaxial layer; and
forming a top gate contact in contact with the extending portion of the bottom gate contact and electrically connecting the bottom gate contact to the BEOL layer.
12 . The method of manufacturing the semiconductor device of claim 11 , wherein the bottom FET includes alternating layers of active semiconductor layers and high-κ metal gate layers.
13 . The method of manufacturing the semiconductor device according to claim 12 , further comprising forming a gate spacer surrounding the high-κ metal gate layers.
14 . The method of manufacturing semiconductor device of claim 11 , further comprising forming a late gate cut insulating layer extending from the top FET to the bottom FET.
15 . The method of manufacturing the semiconductor device of claim 14 , wherein the late gate cut insulating layer electrically isolates the top FET and the bottom FET.
16 . The method of manufacturing the semiconductor device according to claim 11 , wherein the bottom gate contact is formed of a high-κ material.
17 . The method of manufacturing the semiconductor device according to claim 11 , wherein the top gate contact is laterally offset from the top FET and the bottom FET.
18 . The method of manufacturing the semiconductor device according to claim 11 , further comprising forming a first bonding oxide layer at a same level as the bottom gate contact.
19 . The method of manufacturing the semiconductor device according to claim 11 , wherein an active region of the top FET is smaller than an active region of the bottom FET.
20 . The method of manufacturing the semiconductor device according to claim 11 , wherein an active region of the top FET is laterally offset from an active region of the bottom FET.