Semiconductor device and electronic apparatus
Provided is a semiconductor device capable of improving a capacitance density of a capacitive element without decreasing an operating voltage. The semiconductor device includes: a first semiconductor substrate including a first capacitive element portion including at least one capacitive element; a second semiconductor substrate stacked with respect to the first semiconductor substrate; and a second capacitive element portion formed by a metal bonding portion provided on a bonding surface between the first semiconductor substrate and the second semiconductor substrate. The first and second capacitive element portions are connected to each other in parallel.
1 . A semiconductor device, comprising:
a first semiconductor substrate including a first capacitive element portion, wherein the first capacitive element portion includes at least one capacitive element;
a second semiconductor substrate on the first semiconductor substrate; and
a second capacitive element portion that includes a metal bonding portion on a bonding surface between the first semiconductor substrate and the second semiconductor substrate, wherein
the second semiconductor substrate includes a third capacitive element portion,
the third capacitive element portion includes a first plurality of capacitive elements connected in parallel,
the first capacitive element portion is connected in parallel to the second capacitive element portion, and
the second capacitive element portion is connected in parallel to the third capacitive element portion.
2 . The semiconductor device according to claim 1 , wherein
the first capacitive element portion connects a second plurality of capacitive elements in parallel, and
the first plurality of capacitive elements and the second plurality of capacitive elements include at least two of a MOS capacitive element, a comb-shaped wiring capacitive element, a metal insulator metal (MIM) capacitive element, or a poly insulator poly (PIP) capacitive element.
3 . The semiconductor device according to claim 1 , wherein
the metal bonding portion of the second capacitive element portion includes a first metal bonding portion and a second metal bonding portion, and
the first metal bonding portion is opposite to the second metal bonding portion in a direction orthogonal to a stacking direction of the first semiconductor substrate and the second semiconductor substrate.
4 . The semiconductor device according to claim 3 , wherein
the first metal bonding portion has a ring shape, and
the second metal bonding portion is at a center portion of the ring shape.
5 . The semiconductor device according to claim 4 , wherein
the first metal bonding portion and the second metal bonding portion include:
a first metal film on a bonding surface of the first semiconductor substrate, and
a second metal film on a bonding surface of the second semiconductor substrate,
in the first metal bonding portion, an inner diameter of the first metal film is smaller than an inner diameter of the second metal film, and
in the second metal bonding portion, a diameter of the first metal film is smaller than a diameter of the second metal film.
6 . The semiconductor device according to claim 3 , wherein the first metal bonding portion and the second metal bonding portion have a square structure.
7 . The semiconductor device according to claim 1 , further comprising a pixel transistor, wherein
the first semiconductor substrate includes at least one of:
a pixel, or
a peripheral circuit configured to process a signal from the pixel transistor, wherein the pixel transistor is configured to amplify a signal from the pixel, and
the second semiconductor substrate includes other one of the at least one of the pixel or the peripheral circuit.
8 . The semiconductor device according to claim 7 , further comprising a third semiconductor substrate at least one of:
on the first semiconductor substrate and the second semiconductor substrate, or
between the first semiconductor substrate and the second semiconductor substrate, wherein
the pixel includes a photodiode, and
the third semiconductor substrate includes the pixel transistor.
9 . The semiconductor device according to claim 1 , wherein
the first semiconductor substrate further includes at least one of:
a sensor unit including a single photon avalanche diode (SPAD) photodiode, or
a peripheral circuit configured to process a signal from the sensor unit, and
the second semiconductor substrate further includes other of the at least one of the sensor unit or the peripheral circuit.
10 . The semiconductor device according to claim 1 , wherein the second capacitive element portion further includes an in-pixel capacitor.
11 . An electronic apparatus, comprising:
a semiconductor device that includes:
a first semiconductor substrate including a first capacitive element portion, wherein the first capacitive element portion includes at least one capacitive element;
a second semiconductor substrate on the first semiconductor substrate; and
a second capacitive element portion that includes a metal bonding portion on a bonding surface between the first semiconductor substrate and the second semiconductor substrate, wherein
the second semiconductor substrate includes a third capacitive element portion,
the third capacitive element portion includes a first plurality of capacitive elements connected in parallel,
the first capacitive element portion is connected in parallel to the second capacitive element portion, and
the second capacitive element portion is connected in parallel to the third capacitive element portion.
12 . A semiconductor device, comprising:
a pixel transistor;
a first semiconductor substrate that includes:
a first capacitive element portion that includes at least one capacitive element, and
at least one of:
a pixel, or
a peripheral circuit configured to process a signal from the pixel transistor, wherein the pixel transistor is configured to amplify a signal from the pixel;
a second semiconductor substrate on the first semiconductor substrate, wherein the second semiconductor substrate includes other one of the at least one of the pixel or the peripheral circuit; and
a second capacitive element portion that includes a metal bonding portion on a bonding surface between the first semiconductor substrate and the second semiconductor substrate, wherein
the first capacitive element portion is connected in parallel to the second capacitive element portion.