Power-on-reset request functionality in semiconductor devices and power management ICs
A semiconductor circuit is disclosed, comprising: a processor; a supply-voltage terminal arranged to receive a supply voltage; an out-of-range-voltage-detection circuit, coupled to the supply-voltage terminal and configured to output a voltage-out-of-range indicator in response to detecting that the supply voltage is out-of-range; a PWM signal generator configured to generate a PWM signal; a power-on-reset request terminal arranged to output the PWM signal during a normal operation of the processor; and logic circuitry between the signal generator and the POR request terminal and configured to modify the PWM signal in response receiving the voltage-out-of-range indicator. A microcontroller circuit incorporating such a semiconductor circuit, and a PMIC circuit for use in conjunction, are also disclosed.
1 . A semiconductor circuit comprising:
a processor;
a supply-voltage terminal arranged to receive a supply voltage;
an out-of-range-voltage-detection circuit, coupled to the supply-voltage terminal and configured to output a voltage-out-of-range indicator in response to detecting that the supply voltage is out-of-range;
a PWM signal generator configured to generate a PWM signal;
a power-on-reset, POR, request terminal arranged to output the PWM signal during a normal operation of the processor to a POR detector circuit of a power management circuit (PMIC); wherein the POR detection circuit is configured to identify the signal received from the POR request terminal; and
logic circuitry between the PWM signal generator and the POR request terminal and configured to modify the PWM signal in response receiving the voltage-out-of-range indicator to provide an output to the POR request terminal.
2 . The semiconductor circuit of claim 1 ,
wherein the processor comprises the PWM signal generator.
3 . The semiconductor circuit of claim 1 ,
further comprising an error-detection circuit configured to detect an error and output an error indicator in response to detecting an error; and
wherein the logic circuitry is further configured to modify the PWM signal in response to receiving the error indicator.
4 . The semiconductor circuit of claim 3 ,
wherein the processor comprises the error-detection circuit.
5 . The semiconductor circuit of claim 1
wherein the out-of-range-voltage-detection circuit comprises
a high-voltage detection, HVD, circuit configured to detect an over-voltage of the supply voltage, and
a low-voltage detection, LVD, circuit configured to detect an undervoltage of the supply voltage.
6 . The semiconductor circuit of claim 1 ,
wherein the PWM signal generator is configured to provide the PWM signal with a fixed frequency and a fixed duty cycle.
7 . The semiconductor circuit of claim 6 ,
wherein the PWM signal generator comprises a one of a set of registers, and one-time-programmable, OTP, circuit, configured to provide the fixed frequency and a fixed duty cycle.
8 . The semiconductor circuit of claim 6 ,
wherein the PWM signal has a duty cycle which is greater than 50%.
9 . A power management IC (PMIC), comprising
a power-on-reset (POR) request input terminal,
a POR detector circuit coupled to the POR request input terminal, and configured to:
identify a one of a modification of and an interruption to a PWM signal received at the POR request input terminal, and
output a POR request in response to identifying the modification of or interruption to the PWM signal;
wherein the PMIC is configured to be coupled to and provide a supply voltage to a microcontroller integrated circuit (IC);
wherein the microcontroller IC includes,
a supply-voltage terminal configured to receive the supply voltage;
an out-of-range-voltage-detection circuit, coupled to the supply-voltage terminal and configured to output a voltage-out-of-range indicator in response to detecting that the supply-voltage is out-of-range;
a PWM signal generator configured to generate the PWM signal;
the power-on-reset (POR) request output terminal arranged to output the PWM signal to the POR request input terminal of the PMIC during a normal operation of a processor; and
logic circuitry between the PWM signal generator and the POR request output terminal and configured to modify the PWM signal in response receiving the voltage-out-of-range indicator.
10 . The PMIC of claim 9 ,
further comprising a fail-safe finite state machine, FSM, wherein the FSM comprises the POR detector circuit.
11 . The PMIC of claim 9 ,
further comprising an undervoltage-detection circuit, and an overvoltage-detection circuit.
12 . A system comprising: comprising
a microcontroller integrated circuit (IC), and
a power management IC (PMIC);
wherein the microcontroller integrated circuit (IC) is configured to receive a supply voltage from the PMIC, and comprises:
a processor;
a supply-voltage terminal arranged to receive the supply voltage; an out-of-range-voltage-detection circuit, coupled to the supply-voltage terminal and configured to output a voltage-out-of-range indicator in response to detecting that the supply-voltage is out-of-range;
a PWM signal generator configured to generate a PWM signal; a power-on-reset (POR) request terminal arranged to output the PWM signal during a normal operation of the processor; and
logic circuitry between the PWM signal generator and the POR request terminal and configured to modify the PWM signal in response receiving the voltage-out-of-range indicator and to provide the output to the POR request terminal;
wherein the PMIC comprises:
a POR request input terminal, and
a POR detector circuit, coupled to the POR request input terminal, and configured to:
identify a one of a modification of and an interruption to the PWM signal received at the POR request input terminal, and
output a POR request in response to identifying the modification of or interruption to the PWM signal.
13 . The system as claimed in claim 12 ,
wherein the out-of-range-voltage-detection circuit comprises
a high-voltage detection (HVD) circuit configured to detect an over-voltage of the supply voltage, and
a low-voltage detection (LVD) circuit configured to detect an undervoltage of the supply voltage.
14 . A system as claimed in claim 13 ,
wherein the PMIC further comprises an undervoltage-detection circuit and an overvoltage-detection circuit; and
wherein the undervoltage-detection circuit and the overvoltage-detection circuit are configured to be triggered by respective voltages which are lower, and higher than corresponding trigger voltages in the semiconductor device LVD and HVD circuit.