IP Library Granted Patent US 12,494,449
Granted Patent B2
US 12,494,449 · App. 18/332,220 · Granted Dec 9, 2025

Semiconductor device with antenna

Inventors: Junya Ikeda (Atsugi, JP); Yoshihiro Nakata (Atsugi, JP); Shinya Sasaki (Ebina, JP)
Assignee: Fujitsu Limited
H01L24/20H01L21/56H01L23/3128H01L23/66H01L24/19H01Q1/2283H05K1/0204H01L23/295H01L23/296H01L2223/6672H01L2223/6677H01L2224/19H01L2224/211H01L2224/215H01L2924/01029H01L2924/14215
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Quick Facts
Patent No.
US 12,494,449
App. No.
18/332,220
Granted
Dec 9, 2025
Kind
B2
Abstract

A semiconductor device with an antenna includes a heat sink having first and second surfaces, a semiconductor chip provided on the second surface and having a circuit surface, a wiring board having a laminate of alternately disposed insulating layers and interconnect layers, and covering side surfaces of the heat sink and the semiconductor chip and the circuit surface, and exposing the first surface, and an antenna provided on the wiring board. The wiring board includes a board connecting part provided on an opposite side from the antenna, a first interconnect electrically connecting the board connecting part and a first terminal provided on the circuit surface, and a second interconnect electrically connecting the antenna and a second terminal provided on the circuit surface.

Claims (35)

1 . A semiconductor device with an antenna, comprising:

a heat sink having a first surface, and a second surface located on an opposite side from the first surface;

a semiconductor chip provided on the second surface of the heat sink, and having a circuit surface located on an opposite side from a surface thereof directly opposing the second surface of the heat sink;

a wiring board having a first board surface located at a position closer to the first surface than to the second surface of the heat sink, a second board surface located on an opposite side from the first board surface, and a laminate of alternately disposed insulating layers and interconnect layers,

wherein the wiring board covers a side surface of the heat sink, and a side surface and the circuit surface of the semiconductor chip, and exposes the first surface of the heat sink at the first board surface; and

an antenna provided on the second board surface of the wiring board,

wherein the wiring board further includes

a board connecting part provided on the first board surface,

a first interconnect configured to electrically connect the board connecting part and a first terminal provided on the circuit surface of the semiconductor chip, and

a second interconnect configured to electrically connect the antenna and a second terminal provided on the circuit surface of the semiconductor chip.

2 . The semiconductor device with the antenna as claimed in claim 1 , further comprising:

a plurality of connection terminals of identical types,

wherein the plurality of connection terminals is provided on the board connecting part of the first board surface, and on the first surface of the heat sink.

3 . The semiconductor device with the antenna as claimed in claim 2 , wherein the plurality of connection terminals includes a first ball grid array and a second ball grid array of identical types.

4 . A combination comprising:

the semiconductor device with the antenna as claimed in claim 3 ; and

a radio frequency board including

a second heat sink directly connected to the first ball grid array, and

a third terminal electrically connected to the board connecting part via the second ball grid array,

wherein the heat sink, the first ball grid array, and the second heat sink form a heat dissipation path for heat generated from the semiconductor chip.

5 . The combination as claimed in claim 4 , wherein the wiring board further includes a matching circuit formed by one or more interconnect layers of the interconnect layers, located at a position closest to the first board surface among all of the interconnect layers, and vias.

6 . The semiconductor device with the antenna as claimed in claim 1 , wherein

the second surface of the heat sink overlaps an entirety of the semiconductor chip in a plan view,

a size of the second surface is greater than or equal to a size of the semiconductor chip in the plan view, and

a size of the first surface of the heat sink is greater than the size of the semiconductor chip in the plan view.

7 . The semiconductor device with the antenna as claimed in claim 1 , further comprising:

a heat conducting member provided between the semiconductor chip and the heat sink,

wherein the heat conducting member has a hardness lower than hardnesses of the heat sink and the semiconductor chip.

8 . The semiconductor device with the antenna as claimed in claim 1 , wherein the wiring board is formed by redistribution layers.

9 . The semiconductor device with the antenna as claimed in claim 8 , wherein

the insulating layers of the wiring board are formed of a resin, and

the interconnect layers of the wiring board are formed of a metal.

10 . The semiconductor device with the antenna as claimed in claim 9 , wherein the heat sink and one of the interconnect layers of the wiring board, located at identical height positions such that the second surface of the heat sink and a surface of the one of the interconnect layers coincide, are formed of identical metal materials.

11 . The semiconductor device with the antenna as claimed in claim 1 , wherein one insulating layer of the insulating layers of the wiring board, located at a height position identical to a height position of the semiconductor chip such that a surface of the one insulating layer and the first board surface of the wiring board coincide, has a largest thickness among the insulating layers.

12 . The semiconductor device with the antenna as claimed in claim 1 , wherein the antenna is provided on the second board surface of the wiring board at a plurality of locations in a plan view.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2026
From: FUJITSU LIMITED
To: 1FINITY INC.
Reel/Frame 073602/0562 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2023
From: IKEDA, JUNYA; NAKATA, YOSHIHIRO; SASAKI, SHINYA
To: FUJITSU LIMITED
Reel/Frame 063913/0920 →
Priority Claims (1)
JP 2022-145101 · Sep 13, 2022 · national
Continuity (1)
Related Publication 20240088083A1 · Mar 14, 2024
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