IP Library Granted Patent US 12,495,490
Granted Patent B2
US 12,495,490 · App. 18/203,295 · Granted Dec 9, 2025

Printed circuit board and manufacturing method thereof

Inventors: Young Kuk Ko (Suwon-si, KR); Sanghoon Kim (Suwon-si, KR); Jiho Yoon (Suwon-si, KR); Gyumook Kim (Suwon-si, KR); Taehun Kim (Suwon-si, KR)
Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
H05K1/0298H05K1/183H05K1/185H05K1/115
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Quick Facts
Patent No.
US 12,495,490
App. No.
18/203,295
Granted
Dec 9, 2025
Kind
B2
Abstract

A printed circuit board: a first insulation layer; a first wiring layer embedded in the first insulation layer; a first via layer disposed in a first via of the first insulation layer; a second insulation layer disposed on the first insulation layer; a second wiring layer embedded in the second insulation layer; a second via layer disposed in a second via of the second insulation layer; and a cavity disposed in the first insulation layer and a portion of the second insulation layer. The cavity includes a first portion and a second portion disposed in the first insulation layer and having different widths, the first portion is disposed at a lateral side of the first wiring layer, the second portion is disposed at a lateral side of the first via layer, and a first width of the first portion is greater than a second width of the second portion.

Claims (59)

1 . A printed circuit board comprising: a first insulation layer; a first wiring layer embedded in the first insulation layer; a first via layer disposed in a first via in the first insulation layer; a second insulation layer disposed on the first insulation layer; a second wiring layer embedded in the second insulation layer; a second via layer disposed in a second via in the second insulation layer; and a cavity disposed in the first insulation layer and a portion of the second insulation layer, wherein the cavity includes a first portion and a second portion disposed in the first insulation layer and having different widths, the first portion is disposed at a lateral side of the first wiring layer and the second portion is disposed at a lateral side of the first via layer, and a first width of the first portion is greater than a second width of the second portion, and the second portion and the entire first via layer are tapered in a same direction in a cross-sectional view of the printed circuit board.

2 . The printed circuit board of claim 1 , wherein

the cavity further includes a third portion disposed in the portion of the second insulation layer, and

the third portion is disposed at a lateral side of the second wiring layer.

3 . The printed circuit board of claim 2 , wherein

a depth of the third portion is substantially equivalent to a thickness of the second wiring layer.

4 . The printed circuit board of claim 2 , wherein

a third width of the third portion is substantially equivalent to the first width.

5 . The printed circuit board of claim 2 , further comprising

a solder resist layer disposed below the first insulation layer,

wherein the cavity further includes a fourth portion in the solder resist layer, and

a fourth width of the fourth portion is greater than the first width and the second width.

6 . The printed circuit board of claim 1 , wherein

a depth of the first portion is substantially equivalent to a thickness of the first wiring layer, and a depth of the second portion is substantially equivalent to a thickness of the first via layer.

7 . The printed circuit board of claim 1 , wherein

the first wiring layer is connected to the second wiring layer through the first via layer.

8 . The printed circuit board of claim 1 , further comprising

a third insulation layer disposed between the first insulation layer and the second insulation layer,

wherein the cavity further includes a fifth portion and a sixth portion disposed in the third insulation layer and having different widths.

9 . The printed circuit board of claim 8 , further comprising

a third wiring layer embedded in the third insulation layer; and

a third via layer disposed in a third via of the third insulation layer,

wherein the fifth portion is disposed at a lateral side of the third wiring layer and the sixth portion is disposed at a lateral side of the third via layer.

10 . The printed circuit board of claim 8 , further comprising

a plurality of protrusions protruding toward the cavity from the second insulation layer.

11 . The printed circuit board of claim 1 , further comprising a plurality of protrusions protruding toward the cavity from the second insulation layer.

12 . The printed circuit board of claim 1 , wherein

the first portion and the second portion of the cavity have a step.

13 . A printed circuit board comprising: a first insulation layer; a first wiring layer embedded in the first insulation layer; a first via layer disposed in a first via in the first insulation layer; a second insulation layer disposed on the first insulation layer; a second wiring layer embedded in the second insulation layer; a second via layer disposed in a second via of the second insulation layer; and a cavity including a first portion penetrating the first insulation layer and a second portion disposed in the second insulation layer, wherein the second portion of the cavity is disposed at a lateral side of the second wiring layer, and a depth of the second portion of the cavity is substantially equivalent to a thickness of the second wiring layer, the first portion comprises a portion disposed at a lateral side of the first via layer, and the portion of the first portion and the entire first via layer are tapered in a same direction in a cross-sectional view of the printed circuit board.

14 . The printed circuit board of claim 13 , wherein the first portion and the second portion of the cavity have a step.

15 . The printed circuit board of claim 13 , further comprising

a plurality of protrusions protruding toward the cavity from the second insulation layer.

16 . The printed circuit board of claim 1 , wherein

the second portion and the first via layer are tapered in the same direction from a bottom of the cavity to the first portion of the cavity.

17 . A printed circuit board comprising:

a first insulation layer;

a first wiring layer embedded in the first insulation layer;

a first via layer disposed in a first via in the first insulation layer;

a second insulation layer disposed on the first insulation layer;

a second wiring layer embedded in the second insulation layer;

a second via layer disposed in a second via in the second insulation layer;

a solder resist layer disposed below the first insulation layer; and

a cavity disposed in the first insulation layer and a portion of the second insulation layer,

wherein the cavity includes a first portion and a second portion disposed in the first insulation layer and having different widths,

the first portion is disposed at a lateral side of the first wiring layer and the second portion is disposed at a lateral side of the first via layer,

a first width of the first portion is greater than a second width of the second portion,

the cavity further includes another portion in the solder resist layer, and

a width of the another portion of the cavity is greater than the first width and the second width.

18 . The printed circuit board of claim 17 , wherein

the cavity further includes a third portion disposed in the portion of the second insulation layer, and

the third portion is disposed at a lateral side of the second wiring layer.

19 . The printed circuit board of claim 18 , wherein

a depth of the third portion is substantially equivalent to a thickness of the second wiring layer.

20 . The printed circuit board of claim 18 , wherein

a third width of the third portion is substantially equivalent to the first width.

21 . The printed circuit board of claim 17 , wherein

a depth of the first portion is substantially equivalent to a thickness of the first wiring layer, and a depth of the second portion is substantially equivalent to a thickness of the first via layer.

22 . The printed circuit board of claim 17 , wherein

the first wiring layer is connected to the second wiring layer through the first via layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2023
From: KO, YOUNG KUK; KIM, SANGHOON; YOON, JIHO; KIM, GYUMOOK; KIM, TAEHUN
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 063797/0485 →
Priority Claims (1)
KR 10-2022-0132348 · Oct 14, 2022 · national
Continuity (1)
Related Publication 20240130051A1 · Apr 18, 2024
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