Dynamic peripheral component interconnect-express performance management
An information handling system detects transmission of input/output data, and enables a data direct input/output capability associated with a PCIe port based on the PCIe performance policy. The system performs a direct memory access transfer of the input/output data to a cache based on the PCIe performance policy, wherein the input/output data is transferred through the PCIe port with the data direct input/output capability.
1 . A method comprising:
detecting, by a processor of an information handling system, transmission of input/output data;
enabling a data direct input/output capability associated with a peripheral component interconnect-express (PCIe) port based on a type of the input/output data and an application type;
performing a direct memory access transfer of the input/output data to a cache based on the type of the input/output data and the application type, wherein the direct memory access transfer of the input/output data is through the PCIe port with the data direct input/output capability; and
modifying a PCIe setting based on the type of the input/output data and the application type associated with the input/output data, wherein the modifying of the PCIe setting is performed by programming a chipset register associated with a PCIe configuration setting, and wherein the modifying of the PCIe setting includes if the input/output data is an audio recording, then turn off a PCIe lane of an inactive PCIe port.
2 . The method of claim 1 , further comprising indexing the input/output data.
3 . The method of claim 1 , further comprising scanning the input/output data.
4 . The method of claim 1 , further comprising mapping of operating system performance to PCIe performance settings.
5 . The method of claim 1 , wherein if the input/output data is isochronous, then the input/output data is transferred to a memory-side cache.
6 . The method of claim 1 , wherein if the input/output data is asynchronous, then the input/output data is transferred to a last-level cache.
7 . The method of claim 1 , wherein if the input/output data is synchronous, then the input/output data is transferred to a last-level cache.
8 . The method of claim 1 , further comprising modifying a user-selectable thermal table mode.
9 . An information handling system, comprising:
a memory to store a peripheral component interconnect-express (PCIe) performance policy; and
a processor to communicate with the memory, the processor to:
detect transmission of input/output data;
enable a data direct input/output capability associated with a PCIe port based on the PCIe performance policy; and
perform a direct memory access transfer of the input/output data to a cache based on the PCIe performance policy, wherein the input/output data is transferred through the PCIe port with the data direct input/output capability, wherein if the input/output data is isochronous, then the input/output data is transferred to a memory-side cache.
10 . The information handling system of claim 9 , wherein the processor is further configured to modify a PCIe setting based on a type of the input/output data and application type associated with the input/output data.
11 . The information handling system of claim 10 , wherein the processor is configured to modify the PCIe setting by programming a chipset register associated with a PCIe configuration setting.
12 . The information handling system of claim 10 , wherein to modify the PCIe setting includes if the input/output data is an audio recording, then turn off a PCIe lane of an inactive PCIe port.
13 . The information handling system of claim 9 , wherein if the input/output data is asynchronous, then the input/output data is transferred to a last-level cache.
14 . The information handling system of claim 9 , wherein if the input/output data is synchronous, then the input/output data is transferred to a last-level cache.
15 . A non-transitory computer-readable medium to store instructions that are executable to perform operations comprising:
detecting transmission of input/output data;
enabling a data direct input/output capability associated with a peripheral component interconnect-express (PCIe) port based on a type of the input/output data and an application type; and
performing a direct memory access transfer of the input/output data to a cache based on the type of the input/output data and the application type, wherein the input/output data is transferred through the PCIe port with the data direct input/output capability, wherein if the input/output data is isochronous, then the input/output data is transferred to a memory-side cache.
16 . The non-transitory computer-readable medium of claim 15 , wherein the operations further comprise modifying a PCIe setting based on the type of the input/output data and the application type associated with the input/output data.
17 . The non-transitory computer-readable medium of claim 16 , wherein the modifying of the PCIe setting is performed by programming a chipset register associated with a PCIe configuration setting.
18 . The non-transitory computer-readable medium of claim 16 , wherein the modifying of the PCIe setting includes if the input/output data is an audio recording, then turn off a PCIe lane of an inactive PCIe port.
19 . The non-transitory computer-readable medium of claim 15 , wherein if the input/output data is asynchronous, then the input/output data is transferred to a last-level cache.
20 . The non-transitory computer-readable medium of claim 15 , wherein if the input/output data is synchronous, then the input/output data is transferred to a last-level cache.