Image processing array with multi-path relay channel for relaying data between relay ports of data processors
A method of calculating warp results, the method may include executing, for each target pixel out of a group of target pixels, a warp calculation process that comprises: receiving, by a first group of processing units of an array of processing units, a first weight and a second weight associated with the target pixel; receiving, by a second group of processing units of the array, values of neighboring source pixels associated with the target pixel; calculating, by the second group, a warp result based on it response to values of the neighboring source pixels and the pair of weights; and providing the warp result to a memory module.
1 . A data processing module comprising:
an array of data processors comprising multiple data processors;
wherein:
each data processor of the multiple data processors is directly coupled to certain data processors of the array;
each data processor of the multiple data processors is indirectly coupled to given data processors that differ from the certain data processors and belong to the array of data processors; and
each data processor of the multiple data processors comprises relay ports and a relay channel for relaying data between the relay ports, wherein the relay channel of each data processor of the multiple data processors comprises (i) a first path that consists of a single multiplexer and exhibits substantially zero latency, (ii) a second path that consists of a multiplexer and a flip flop, (iii) a third path that consists of two multiplexers, and (iv) a fourth path that consists of two multiplexers and a flip flop.
2 . The data processing module according to claim 1 , wherein the first path, the second path, the third path, and the fourth path of the relay channel of each data processor of the multiple data processors are coupled in parallel.
3 . The data processing module according to claim 1 , wherein each data processor of the multiple data processors comprises a core; wherein the core comprises an arithmetic logic unit and a memory resource; wherein a number of cores of a number of data processors of the multiple data processors are coupled to each other by a configurable network.
4 . The data processing module according to claim 3 , wherein each data processor of the multiple data processors comprises multiple data flow components of the configurable network.
5 . The data processing module according to claim 1 , wherein each data processor of the multiple data processors comprises a first non-relay input port that is directly coupled to data processors of a first set of neighboring data processors.
6 . The data processing module according to claim 5 , wherein for each particular data processor of the multiple data processors, the first set of neighboring data processors is formed by data processors that are located within a distance less than four data processors from the particular data processor.
7 . The data processing module according to claim 5 , wherein for each particular data processor of the multiple data processors, the first non-relay input port of the particular data processor is directly coupled to relay ports of data processors of the first set of neighboring data processors.
8 . The data processing module according to claim 7 , wherein each data processor of the multiple data processors further comprises a second non-relay input port that is directly coupled to non-relay ports of data processors of the first set of neighboring data processors.
9 . The data processing module according to claim 5 , wherein for each particular data processor of the multiple data processors, the first non-relay input port of the particular data processor is directly coupled to non-relay ports of data processors of the first set of neighboring data processors.
10 . The data processing module according to claim 5 , wherein the first set of neighboring data processors is formed by eight data processors.
11 . The data processing module according to claim 5 , wherein a first relay port of each data processor of the multiple data processors is directly coupled to a second set of neighboring data processors.
12 . The data processing module according to claim 11 , wherein for each data processor of the multiple data processors, the second set of neighboring data processors differs from the first set of neighboring data processors.
13 . The data processing module according to claim 11 , wherein for each particular data processor of the multiple data processors, the second set of neighboring data processors comprises a data processor that is more distant from the particular data processor than any of the data processors that belong to the first set of neighboring data processors.
14 . The data processing module according to claim 1 , wherein the array of data processors comprises, in addition to the multiple data processors, at least one other data processor.
15 . The data processing module according to claim 1 , wherein data processors of the array of data processors are arranged in rows and columns.
16 . The data processing module according to claim 15 , wherein the data processors of each row are coupled to each other in a cyclic manner.
17 . The data processing module according to claim 15 , wherein data processors of each row are controlled by a shared microcontroller.
18 . The data processing module according to claim 15 , wherein each data processor of the multiple data processors comprises configuration instruction registers;
wherein the configuration instruction registers are arranged to receive configuration instructions during a configuration process and to store the configuration instructions;
wherein data processors of a given row are controlled by a given shared microcontroller; and
wherein each data processor of the given row is arranged to:
receive selection information for selecting a selected configuration instruction from the given shared microcontroller; and
configure, under a certain condition, itself to operate according to the selected configuration instruction.
19 . The data processing module according to claim 18 , wherein the certain condition is fulfilled when the data processing module is arranged to respond to the selection information; wherein the certain condition is not fulfilled when each data processor of the given row is arranged to ignore the selection information.
20 . The data processing module according to claim 1 , wherein each data processor of the multiple data processors comprises a controller, an arithmetic logic unit, a register file, and configuration instruction registers; wherein the configuration instruction registers are arranged to receive configuration instructions during a configuration process and to store the configuration instructions in the configuration instruction registers; wherein the controller is arranged to receive selection information for selecting a selected configuration instruction to configure a respective data processor to operate according to the selected configuration instruction.
21 . The data processing module according to claim 20 , wherein each data processor of the multiple data processors comprises up to three configuration instruction registers.
22 . The data processing module according to claim 1 , wherein the multiple data processors comprise a first group of data processors and a second group of data processors;
wherein a first data processor of the first group of data processors is configured to generate a first calculation result; and
wherein a second data processor of the second group of data processors is configured to generate a second calculation result based on the first calculation result.
23 . A method for operating a processing module, the method comprising:
processing data by an array of data processors; and
relaying data, using relay channels of data processors of the array;
wherein:
the array comprises multiple data processors included in a processing module;
each data processor of the multiple data processors is directly coupled to certain data processors of the array;
the multiple data processors comprise a first group of data processors and a second group of data processors;
a first data processor of the first group of data processors is configured to generate a first calculation result;
each data processor of the multiple data processors is indirectly coupled to given data processors that differ from the certain data processors and belong to the array of data processors,
a second data processor of the second group of data processors is configured to generate a second calculation result based on the first calculation result; and
each data processor of the multiple data processors comprises relay ports and a relay channel for relaying data between the relay ports, wherein the relay channel of each data processor of the multiple data processors comprises (i) a first path that consists of a single multiplexer and exhibits substantially zero latency, (ii) a second path that consists of a multiplexer and a flip flop, (iii) a third path that consists of two multiplexers, and (iv) a fourth path that consists of two multiplexers and a flip flop.
24 . The method according to claim 23 , wherein the first path, the second path, the third path, and the fourth path of the relay channel of each data processor of the multiple data processors are coupled in parallel.
25 . A first data processor, the first data processor being one of multiple data processors in an array of data processors, the first data processor comprising:
a first port to provide direct communication with a second data processor of the array of data processors, the second data processor directly coupled to the first data processor;
a second port to provide indirect communication with a third data processor of the array of data processors, the third data processor indirectly coupled to the first data processor; and
a relay channel, the relay channel including an input relay port and an output relay port, the relay channel to relay data between two data processors directly coupled to the first data processor;
wherein the relay channel comprises (i) a first path that consists of a single multiplexer and exhibits substantially zero latency, (ii) a second path that consists of a multiplexer and a flip flop, (iii) a third path that consists of two multiplexers, and (iv) a fourth path that consists of two multiplexers and a flip flop.
26 . The first data processor of claim 25 , further comprising a first non-relay input port that is directly coupled to data processors of a first set of neighboring data processors.
27 . The first data processor of claim 26 , wherein the first set of neighboring data processors is formed by data processors that are located with a distance less than four data processors from the first data processor.