IP Library Granted Patent US 12,499,079
Granted Patent B2
US 12,499,079 · App. 18/421,686 · Granted Dec 16, 2025

Apparatus including reconfigurable interface and methods of manufacturing the same

Inventors: Won Joo Yun (Boise, ID); Sang-Hoon Shin (Boise, ID)
Assignee: Micron Technology, Inc.
G06F15/7871G06F15/7892G11C7/1057G11C7/1084
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Quick Facts
Patent No.
US 12,499,079
App. No.
18/421,686
Granted
Dec 16, 2025
Kind
B2
Abstract

An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. A reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.

Claims (50)

1 . A semiconductor device, comprising:

an external interface connector;

an output buffer coupled to the external interface connector and a variable driver voltage, the output buffer configured to generate output signals based on the variable driver voltage, wherein the output signals are sent through the external interface connector;

an input buffer coupled to the external interface connector and a variable signal reference, the input buffer configured to receive input signals through the external interface connector, wherein the input signals are received based on the variable signal reference; and

a control circuit configured to selectively configure the variable driver voltage or the variable signal reference.

2 . The semiconductor device of claim 1 , wherein the control circuit is configured to control the variable driver voltage, the variable signal reference, or a combination thereof to implement (1) a multi-drop communication configuration or a point-to-point communication configuration, (2) an input communication path and/or an output communication path through the external interface connector, (3) a terminated path or a non-terminated path through the external interface connector, (4) a single-ended communication configuration or a complementary communication configuration, or a combination thereof.

3 . The semiconductor device of claim 2 , wherein the control circuit is configured to selectively configure a communication setting for signals exchanged through the external interface connector to implement (1) the multi-drop communication configuration, (2) the input communication path without the output communication path, (3) the terminated path, and (4) the single-ended communication configuration.

4 . The semiconductor device of claim 3 , wherein the control circuit is configured to selectively configure a communication setting for signals exchanged through the external interface connector based on (a) activating a terminated circuit in the output buffer, (b) activating the input buffer, (c) controlling the variable driver voltage to provide a system voltage, and (d) controlling a variable reference generator to receive up to the system voltage, wherein the variable reference generator is configured to provide the variable signal reference.

5 . The semiconductor device of claim 2 , wherein the control circuit is configured to selectively configure a communication setting for signals exchanged through the external interface connector to implement (1) the point-to-point communication configuration, (2) the input communication path without the output communication path, (3) the non-terminated path, and (4) the single-ended communication configuration.

6 . The semiconductor device of claim 5 , wherein the control circuit is configured to selectively configure the communication setting based on (a) deactivating the output buffer, (b) activating the input buffer, (c) controlling the variable driver voltage to provide an open setting, and (d) controlling a variable reference generator to receive up to a reduced voltage less than a system voltage, wherein the variable reference generator is configured to provide the variable signal reference.

7 . The semiconductor device of claim 2 , wherein the control circuit is configured to selectively configure a communication setting for signals exchanged through the external interface connector to implement (1) the multi-drop communication configuration, (2) both input and output communication paths through the connector, (3) the terminated path, and (4) the single-ended communication configuration.

8 . The semiconductor device of claim 7 , wherein the control circuit is configured to selectively configure the communication setting based on (a) activating both a pull-up driver and a pull-down driver in the output buffer, (b) activating the input buffer, (c) controlling the variable driver voltage to provide a system voltage, and (d) controlling a variable reference generator to receive up to the system voltage, wherein the variable reference generator is configured to provide the variable signal reference.

9 . The semiconductor device of claim 2 , wherein:

the external interface connector comprises a first connector configured to communicate first signals with an external circuit;

the input buffer includes a signal port and a reference port, the input buffer configured to receive the input signals based on comparing voltages at the signal port and the reference port;

further comprising:

a second connector configured to communicate second signals with the external circuit; and

a coupling mechanism connected between (1) the first connector and the signal port of the input buffer and (2) a variable reference generator and the reference port of the input buffer, the coupling mechanism selectively operable to couple the input buffer to the second connector for implementing the complementary communication configuration, wherein the first and second signals are complementary signals that correspond to a single stream of information and wherein the variable reference generator is configured to provide the variable signal reference.

10 . The semiconductor device of claim 9 , wherein:

the control circuit is configured to operate the coupling mechanism to couple the reference port of the input buffer to the second connector; and

a first output source, a first output buffer, a first variable reference generator, a first input buffer, a first coupling mechanism, and a first control circuit comprise a first reconfigurable interface circuit configured to selectively configure a first communication setting for signals exchanged through the for the first connector;

further comprising:

a second reconfigurable interface circuit including a second output source, a second output buffer, a second variable reference generator, a second input buffer, a second coupling mechanism, and a second control circuit, the second reconfigurable interface circuit configured to selectively configure a second communication setting for signals exchanged through the second connector, wherein the second control circuit is configured to operate the second coupling mechanism connect the second connector to the first input buffer instead of the second input buffer for the complementary communication configuration.

11 . The semiconductor device of claim 10 , wherein the first and second control circuits are each configured to configure a communication setting for signals exchanged through each of the first and second control circuits to implement (1) the multi-drop communication configuration, (2) the input communication paths without the output communication paths, (3) the terminated paths for the first and second connectors along with the complementary communication configuration.

12 . The semiconductor device of claim 1 , wherein the control circuit is configured to selectively provide at least a system voltage, a reduced voltage less than the system voltage, and an open circuit setting.

13 . The semiconductor device of claim 1 , wherein:

the output buffer includes

a pull-up driver configured to selectively generate the output signals;

a pull-down driver configured to selectively generate the output signals; and

the control circuit is configured to activate the pull-up driver, the pull-down driver, or both according to a communication setting for signals exchanged through the external interface connector.

14 . The semiconductor device of claim 13 , wherein the pull-up driver includes an on-die termination circuit.

15 . The semiconductor device of claim 1 , further comprising:

a configuration source configured to store a communication setting for signals exchanged through the external interface connector; and

wherein:

the control circuit comprises a logic configured to access the communication setting and control according to the accessed communication setting the variable driver voltage, the output buffer, a variable reference generator, the input buffer, or a combination thereof, wherein the variable reference generator is configured to provide the variable signal reference.

16 . The semiconductor device of claim 1 , wherein the semiconductor device comprises a high-speed memory (HBM) device.

17 . The semiconductor device of claim 16 , wherein the HBM comprises a system-in-package (SiP) device that further includes a processor coupled to the HBM.

18 . The semiconductor device of claim 17 , wherein the external interface connector is a direct access connector configured to facilitate exchange of information directly between an external device and the HBM without communicating through the processor.

19 . A method of operating a semiconductor device, the method comprising:

selectively controlling, based on a communication setting for the semiconductor device, one or more components of the semiconductor device to select (1) a multi-drop communication configuration or a point-to-point communication configuration, (2) an input communication path and/or an output communication path, (3) a terminated path or a non-terminated path, (4) a single-ended communication configuration or a complementary communication configuration, or a combination thereof for communicated signals,

wherein the one or more components includes:

an output buffer configured to generate output signals based on a variable driver voltage, the variable driver voltage set to one of at least two voltages;

an input buffer configured to receive input signals from an external circuit according to a variable reference; or

the variable reference set to provide a reading range up to the one of at least two voltages;

wherein the input buffer is connected to a first connector configured to receive a first signal; and

wherein selectively controlling the one or more components includes:

controlling an operating state of the one or more components configured to generate or receive communicated signals;

selectively changing, based on the communication setting for the semiconductor device, the selected communication configuration for the semiconductor device;

disconnecting the input buffer from the variable reference; and

connecting the input buffer to a second connector instead of the variable reference, wherein the second connector is configured to receive a second signal that is complementary to the first signal for communicating a single stream of information.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2024
From: YUN, WON JOO; SHIN, SANG-HOON
To: MICRON TECHNOLOGY, INC.
Reel/Frame 066236/0260 →
Continuity (2)
Continuation 17398863 · Aug 10, 2021
Related Publication 20240160600A1 · May 16, 2024
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