Semiconductor device including guard ring
A semiconductor device includes: a semiconductor substrate; and a guard ring including a plurality of conductive patterns stacked over the semiconductor substrate in a first direction to be spaced apart from each other, and a conductive plug disposed between two adjacent conductive patterns among the plurality of conductive patterns, the first direction being perpendicular to a top surface of the semiconductor substrate, wherein the conductive plug includes a plurality of long patterns and a plurality of short patterns.
1 . A semiconductor device comprising:
a semiconductor substrate; and
a guard ring including a plurality of conductive patterns stacked over the semiconductor substrate in a first direction to be spaced apart from each other, and a conductive plug disposed between two adjacent conductive patterns among the plurality of conductive patterns, the first direction being perpendicular to a top surface of the semiconductor substrate,
wherein the conductive plug includes a plurality of long patterns and a plurality of short patterns, the plurality of long patterns extending in a second direction to be parallel to each other and spaced apart from each other in a third direction, the plurality of short patterns extending in the third direction, disposed between two adjacent long patterns among the plurality of long patterns to connect the two adjacent long patterns, and spaced apart from each other in the second direction, the second direction crossing the third direction, the second and third directions being parallel to the top surface of the semiconductor substrate, and
wherein an internal insulating layer, which has a side surface that is surrounded by the two adjacent long patterns and two adjacent short patterns among the plurality of short patterns, is connected to at least one of an external insulating layer and another internal insulating layer through an open portion disposed in at least one of the two adjacent long patterns, the external insulating layer positioned outside the conductive plug.
2 . The semiconductor device according to claim 1 , wherein the plurality of long patterns include first to third long patterns,
the plurality of short patterns include a plurality of first short patterns connecting the first long pattern and the second long pattern, and a plurality of second short patterns connecting the second long pattern and the third long pattern,
the internal insulating layer includes a first internal insulating layer having a side surface surrounded by the first long pattern, the second long pattern, and two adjacent first short patterns among the plurality of first short patterns, and a second internal insulating layer having a side surface surrounded by the second long pattern, the third long pattern, and two adjacent second short patterns among the plurality of second short patterns, and
the open portion includes at least one of a first open portion disposed in the first long pattern, a second open portion disposed in the third long pattern, and a third open portion disposed in the second long pattern.
3 . The semiconductor device according to claim 2 , wherein the first internal insulating layer is connected to the external insulating layer through the first open portion, and
the second internal insulating layer is connected to the external insulating layer through the second open portion.
4 . The semiconductor device according to claim 2 , wherein the first internal insulating layer and the second internal insulating layer are connected to each other through the third open portion.
5 . The semiconductor device according to claim 2 , wherein the first internal insulating layer is connected to the external insulating layer through the first open portion,
the second internal insulating layer is connected to the external insulating layer through the second open portion, and
the first internal insulating layer and the second internal insulating layer are connected to each other through the third open portion.
6 . The semiconductor device according to claim 2 , wherein the first open portion is positioned between the two adjacent first short patterns among the plurality of first short patterns, and the second open portion is positioned between the two adjacent second short patterns among the plurality of second short patterns.
7 . The semiconductor device according to claim 2 , wherein the third open portion is positioned between one first short pattern of the plurality of first short patterns and one second short pattern of the plurality of second short patterns, the one first short pattern being adjacent to the one second short pattern.
8 . The semiconductor device according to claim 2 , wherein a second short pattern among the plurality of second short patterns is positioned between the two adjacent first short patterns among the plurality of first short patterns, and
a first short pattern among the plurality of first short patterns is positioned between the two adjacent second short patterns among the plurality of second short patterns.
9 . The semiconductor device according to claim 1 , wherein the semiconductor substrate includes a first region in which an integrated circuit is disposed, and a second region in which the guard ring is disposed.
10 . The semiconductor device according to claim 9 , wherein the plurality of conductive patterns and the plurality of long patterns each have a loop shape surrounding the first region.
11 . The semiconductor device according to claim 9 , wherein at least one of the plurality of conductive patterns includes an inner conductive pattern having a loop shape surrounding the first region, and an outer conductive pattern having a loop shape surrounding the inner conductive pattern.
12 . The semiconductor device according to claim 11 , wherein the conductive plug includes an inner conductive plug and an outer conductive plug, the inner conductive plug and the outer conductive plug overlapping the inner conductive pattern and the outer conductive pattern, respectively, when viewed in a plan view.
13 . A semiconductor device comprising:
a semiconductor substrate; and
a guard ring including a plurality of conductive patterns stacked over the semiconductor substrate in a first direction to be spaced apart from each other, and a conductive plug disposed between two adjacent conductive patterns among the plurality of conductive patterns, the first direction being perpendicular to a top surface of the semiconductor substrate,
wherein the conductive plug includes a plurality of long patterns and a plurality of short patterns, the plurality of long patterns extending in a second direction to be parallel to each other and spaced apart from each other in a third direction, the plurality of short patterns extending in the third direction, disposed between two adjacent long patterns among the plurality of long patterns to connect the two adjacent long patterns, and spaced apart from each other in the second direction, the second direction crossing the third direction, the second and third directions being parallel to the top surface of the semiconductor substrate, and
wherein at least one of the plurality of long patterns has a shape cut between two adjacent short patterns among the plurality of short patterns.
14 . The semiconductor device according to claim 13 , wherein the plurality of long patterns include first to third long patterns,
the plurality of short patterns include a plurality of first short patterns connecting the first long pattern and the second long pattern, and a plurality of second short patterns connecting the second long pattern and the third long pattern, and
the conductive plug includes one or more of a first case in which the first long pattern has a shape cut between two adjacent first short patterns among the plurality of first short patterns, a second case in which the third long pattern has a shape cut between two adjacent second short patterns among the plurality of second short patterns, or a third case in which the second long pattern has a shape cut between one first short pattern of the plurality of first short patterns and one second short pattern of the plurality of second short patterns, which is adjacent to the one first short pattern.
15 . The semiconductor device according to claim 14 , wherein the conductive plug includes the first case and the second case.
16 . The semiconductor device according to claim 14 , wherein the conductive plug includes the third case.
17 . The semiconductor device according to claim 14 , wherein the conductive plug includes the first case, the second case, and the third case.
18 . The semiconductor device according to claim 14 , wherein a first internal insulating layer has a side surface surrounded by the first long pattern, the second long pattern, and the two adjacent first short patterns, and a second internal insulating layer has a side surface surrounded by the second long pattern, the third long pattern, and the two adjacent second short patterns,
the first internal insulating layer and the second internal insulating layer are connected to each other or to an external insulating layer outside the first and third long patterns.
19 . The semiconductor device according to claim 13 , wherein the semiconductor substrate includes a first region in which an integrated circuit is disposed, and a second region in which the guard ring is disposed.
20 . The semiconductor device according to claim 19 , wherein the plurality of conductive patterns and the plurality of long patterns each have a loop shape surrounding the first region.