Granted Patent B2

US 12,536,735 · App. 18/543,753 · Granted Jan 27, 2026

Inventor: Pawel Kozlowski (Truckee, CA)

Assignee: Nvidia Corporation

G06T15/80G06T1/20G06T5/50G06T5/70G06T15/005

Abstract

Claims (44)

1 . A method for reducing temporal lag over a series of frames, comprising:

computing, using a first algorithm, a first value representative of a first list of previous pixel values associated with a pixel in a first frame of the series of frames;

computing, using a second algorithm, a second value representative of a second list of previous pixel values associated with the pixel in a second frame of the series of frames, the second frame occurring before the first frame;

determining a pixel display value based on the first value and the second value;

determining a change in a pixel value above a threshold change rate for the pixel between the first frame and the second frame;

receiving a new pixel value for the pixel to be displayed in a third frame subsequent to the second frame in the series of frames;

updating the first list to include the new pixel value and to remove an oldest pixel value from the first list;

determining a new value representative of the first list using the first algorithm;

updating a display pixel value for the pixel based on the new value; and

causing a display of the third frame using the display pixel value for the pixel.

2 . The method of claim 1 , wherein the first value is a simple moving average.

3 . The method of claim 1 , wherein the second value is an exponential moving average.

4 . The method of claim 1 , further comprising:

determining a dynamic event occurring between the first frame and the second frame.

5 . The method of claim 4 , further comprising:

determining that the dynamic event is complete;

determining an average over the first list using the first algorithm and the second list using the second algorithm.

6 . The method of claim 4 , wherein the dynamic event is movement of a light source in the series of frames.

7 . The method of claim 1 , wherein a size of the first list is based on a frame rate of the series of frames.

8 . The method of claim 1 , further comprising determining a temporal lag between at least the first frame and the second frame, based at least in part on the change in the pixel value occurring above the threshold change rate.

9 . The method of claim 8 , further comprising determining, using at least one additional pixel value, that the temporal lag exceeds a temporal lag threshold.

10 . The method of claim 8 , wherein the new value is determined, based at least in part on the temporal lag between the first frame and the second frame.

11 . The method of claim 1 , wherein updating the display pixel value further comprises using one or more previous pixel values associated with the pixel.

12 . A processor, comprising:

one or more circuits to:

compute, using a first algorithm, a first value representative of a first list of previous pixel values associated with a pixel in a first frame of a series of frames;

compute, using a second algorithm, a second value representative of a second list of previous pixel values associated with the pixel in a second frame of the series of frames, the second frame occurring before the first frame;

determine a pixel display value for the pixel based at least in part on the first value and the second value; and

update the pixel display value for the pixel based at least in part on the first list using the first algorithm.

13 . The processor of claim 12 , wherein the one or more circuits are further to:

receive a new pixel value for the pixel to be displayed in a third frame of the series of frames, the third frame subsequent to the second frame.

14 . The processor of claim 13 , wherein the one or more circuits are further to:

update the first list to include the new pixel value.

15 . The processor of claim 14 , wherein the one or more circuits are further to update the pixel display value for the pixel by determining a new value representative of the first list using the first algorithm.

16 . The processor of claim 12 , wherein the first value is a simple moving average.

17 . The processor of claim 12 , wherein the second value is an exponential moving average.

18 . The processor of claim 12 , wherein the one or more circuits are further to update the pixel display value for the pixel based at least in part on detecting a dynamic event corresponding to the series of frames.

19 . A system, comprising:

one or more processors to update a pixel display value for a pixel based in part on a first list using a first algorithm, a first value, computed using the first algorithm, representative of the first list including previous pixel values associated with the pixel in a first frame of a series of frames, a second value, computed using a second algorithm, representative of a second list of previous pixel values being associated with the pixel in a second frame of the series of frames that occur before the first frame, the pixel display value for the pixel determined based in part on the first value and the second value, wherein an oldest pixel value is removed from the first list.

20 . The system of claim 19 , wherein the one or more processors are further to:

receive a new pixel value for the pixel to be displayed in a third frame of the series of frames, the third frame subsequent to the second frame;

detect a dynamic event corresponding to the series of frames;

update the first list to include the new pixel value; and

determine a new value representative of the first list using the first algorithm.

Continuity (2)

References Cited (23)