Method of operating a memory controller, a memory controller and a memory system
The present disclosure provides a method of operating a memory controller, a memory controller, and a memory system, and relates to the technical field of memories. The memory controller includes an Advanced Encryption Standard (AES) engine, a processor, and a first interface, and the memory controller is communicatively connected with a first memory through the first interface. The method includes: in response to the memory controller being powered on, obtaining, by the processor, firmware from the first memory through the first interface, wherein the firmware includes a configuration information ciphertext of a first trusted computing group (TCG); and decrypting, by the AES engine, the configuration information ciphertext of the first TCG based on a first key and a preset decryption algorithm, to obtain a configuration information plaintext of the TCG.
1 . A method of operating a memory controller, wherein the memory controller comprises an Advanced Encryption Standard (AES) engine, a processor, a second memory, and a first interface, and the memory controller is communicatively connected with a first memory through the first interface, the method comprising:
in response to the memory controller being powered on, obtaining, by the processor, firmware from the first memory through the first interface, wherein the firmware comprises a configuration information ciphertext of a first trusted computing group (TCG);
decrypting, by the AES engine, the configuration information ciphertext of the first TCG based on a first key and a preset decryption algorithm, to obtain a configuration information plaintext of the TCG;
storing, by the processor, the firmware in the second memory; and
determining, by the AES engine, the configuration information ciphertext of the first TCG from the second memory based on a logical address corresponding to the configuration information ciphertext of the first TCG.
2 . The method of claim 1 , wherein the decrypting, by the AES engine, the configuration information ciphertext of the first TCG based on the first key and the preset decryption algorithm, to obtain the configuration information plaintext of the TCG comprises:
performing, by the AES engine, an operation on the configuration information ciphertext of the first TCG through an AES decryption function by using the first key, to obtain the configuration information plaintext of the TCG.
3 . The method of claim 1 , wherein the memory controller further comprises a third memory in which the first key is stored, and the method further comprises:
reading, by the processor, the first key from the third memory.
4 . The method of claim 1 , further comprising:
in response to update of the configuration information plaintext of the TCG, encrypting, by the AES engine, the updated configuration information plaintext of the TCG based on a second key and a preset encryption algorithm, to obtain a configuration information ciphertext of a second TCG; and
storing, by the processor, the firmware comprising the configuration information ciphertext of the second TCG to the first memory.
5 . The method of claim 4 , further comprising:
obtaining, by the processor, the firmware comprising the updated configuration information plaintext of the TCG from the second memory.
6 . The method of claim 4 , wherein the memory controller further comprises a third memory storing the second key, and the method further comprises:
reading, by the processor, the second key from the third memory.
7 . The method of claim 1 , wherein the first memory comprises a non-volatile flash memory.
8 . A memory controller, comprising:
an Advanced Encryption Standard (AES) engine;
a processor;
a second memory; and
a first interface,
wherein:
the memory controller is communicatively connected with a first memory through the first interface;
the processor is configured to, in response to the memory controller being powered on, obtain firmware from the first memory through the first interface and store the firmware in the second memory, wherein the firmware comprises a configuration information ciphertext of a first trusted computing group (TCG); and
the AES engine is configured to:
decrypt the configuration information ciphertext of the first TCG based on a first key and a preset decryption algorithm, to obtain a configuration information plaintext of the TCG; and
determine the configuration information ciphertext of the first TCG from the second memory based on a logical address corresponding to the configuration information ciphertext of the first TCG.
9 . The memory controller of claim 8 , wherein the AES engine is further configured to:
perform an operation on the configuration information ciphertext of the first TCG through an AES decryption function by using the first key, to obtain the configuration information plaintext of the TCG.
10 . The memory controller of claim 8 , further comprising a third memory in which the first key is stored, and the processor is further configured to:
read the first key from the third memory.
11 . The memory controller of claim 8 , wherein the AES engine is further configured to:
in response to update of the configuration information plaintext of the TCG, encrypt the updated configuration information plaintext of the TCG based on a second key and a preset encryption algorithm, to obtain a configuration information ciphertext of a second TCG; and
the processor is further configured to store the firmware comprising the configuration information ciphertext of the second TCG to the first memory.
12 . The memory controller of claim 11 , wherein the processor is further configured to:
obtain the firmware comprising the updated configuration information plaintext of the TCG from the second memory.
13 . The memory controller of claim 11 , further comprising a third memory storing the second key, and the processor is further configured to:
read the second key from the third memory.
14 . The memory controller of claim 8 , wherein the first memory comprises a non-volatile flash memory.
15 . A memory system, comprising:
a memory controller, comprising:
an Advanced Encryption Standard (AES) engine;
a processor;
a second memory; and
a first interface,
wherein:
the memory controller is communicatively connected with a first memory through the first interface;
the processor is configured to in response to the memory controller being powered on, obtain firmware from the first memory through the first interface and store the firmawre in the second memory, wherein the firmware comprises a configuration information ciphertext of a first trusted computing group (TCG); and
the AES engine is configured to:
decrypt the configuration information ciphertext of the first TCG based on a first key and a preset decryption algorithm, to obtain a configuration information plaintext of the TCG; and
determine the configuration information ciphertext of the first TCG from the second memory based on a logical address corresponding to the configuration information ciphertext of the first TCG; and
one or more first memories coupled with the memory controller.
16 . The memory system of claim 15 , wherein the AES engine is further configured to:
perform an operation on the configuration information ciphertext of the first TCG through an AES decryption function by using the first key, to obtain the configuration information plaintext of the TCG.
17 . The memory system of claim 15 , wherein the memory controller further comprises a third memory in which the first key is stored, and the processor is further configured to:
read the first key from the third memory.
18 . The memory system of claim 15 , wherein the AES engine is further configured to:
in response to update of the configuration information plaintext of the TCG, encrypt the updated configuration information plaintext of the TCG based on a second key and a preset encryption algorithm, to obtain a configuration information ciphertext of a second TCG; and
the processor is further configured to store the firmware comprising the configuration information ciphertext of the second TCG to the first memory.
19 . The memory system of claim 18 , wherein the processor is further configured to:
obtain the firmware comprising the updated configuration information plaintext of the TCG from the second memory.
20 . The memory system of claim 18 , further comprising a third memory storing the second key, and the processor is further configured to:
read the second key from the third memory.