IP Library Granted Patent US 12,554,654
Granted Patent B2
US 12,554,654 · App. 18/145,332 · Granted Feb 17, 2026

Selective memory duplication control

Inventor: Jonathan Charles Masters (Boston, MA)
Assignee: Google LLC
G06F12/1408G06F11/1435G06F12/1441
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,554,654
App. No.
18/145,332
Granted
Feb 17, 2026
Kind
B2
Abstract

Generally disclosed herein is an approach for securing data. The approach may include encountering a pointer to a first memory location and determining, based on the pointer, that the first memory location is storing sensitive data. The approach may further include automatically copying the sensitive data to a secure memory location in response to determining that the first memory location is storing sensitive data.

Claims (39)

1 . A method for securing data, comprising:

receiving, by one or more processors, a pointer to a first memory location, wherein the pointer comprises a plurality of bits, wherein a first subset of the plurality of bits identifies an address of the first memory location and a second subset of the plurality of bits indicates that the first memory location stores sensitive data;

determining, by the one or more processors based on the pointer, that the first memory location is storing sensitive data;

copying, by one or more processors, the sensitive data;

storing a copy of the sensitive data to at least one second memory location; and

generating the pointer including a tag for the sensitive data at a time of hardware programming.

2 . The method of claim 1 , wherein the sensitive data includes security keys or permission access keys.

3 . The method of claim 1 , further comprising storing instructions pertaining to microarchitectural behaviors.

4 . The method of claim 1 , wherein the at least one second memory location is in Li or L2 cache.

5 . The method of claim 1 , wherein the tag is associated with instructions for a controller to take one or more actions.

6 . The method of claim 1 , wherein the at least one second memory location is in a memory region that is physically independent from the first memory location.

7 . The method of claim 1 , wherein the at least one second memory location is carved out from an existing cache structure.

8 . The method of claim 1 , further comprising:

accessing the sensitive data at the first memory location;

determining that the sensitive data at the first memory location is missing or corrupted; and

initiating a corrective action when the sensitive data at the first memory location is missing or corrupted.

9 . The method of claim 8 , wherein initiating a corrective action comprises loading the copy of the sensitive data from the second memory location.

10 . The method of claim 8 , wherein the corrective action comprises replacing contents of the first memory location with the copy of the sensitive data from the second memory location.

11 . The method of claim 1 , further comprises:

determining whether the sensitive data is stored in L1 cache;

when the sensitive data is stored in L1 cache, determining that the sensitive data is stored in a secure location; and

in response to determining that the sensitive data is stored in a secure location, taking no further action with respect to copying the sensitive data.

12 . A system for securing data, the system comprising:

one or more memories; and

one or more processors configured to:

receive a pointer to a first memory location, wherein the pointer comprises a plurality of bits, wherein a first subset of the plurality of bits identifies an address of the first memory location and a second subset of the plurality of bits indicates that the first memory location is storing sensitive data;

determine based on the pointer, that the first memory location is storing sensitive data;

copy the sensitive data;

store a copy of the sensitive data to at least one second memory location; and

generate the pointer including a tag for the sensitive data at a time of hardware programming.

13 . The system of claim 12 , wherein the one or more processors are further configured to:

access the sensitive data at the first memory location;

determine that the sensitive data at the first memory location is missing or corrupted; and

initiate a corrective action when the sensitive data at the first memory location is missing or corrupted.

14 . The system of claim 13 , wherein initiate a corrective action comprises loading the copy of the sensitive data from the second memory location.

15 . The system of claim 13 , wherein the corrective action comprises replacing contents of the first memory location with the copy of the sensitive data from the second memory location.

16 . The system of claim 13 , wherein the second memory location is in a memory region that is physically independent from the first memory location.

17 . The system of 14 , wherein the sensitive data comprises security keys or permission access keys.

18 . The system of claim 12 , wherein the second memory location is carved out from an existing cache structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2023
From: MASTERS, JONATHAN CHARLES
To: GOOGLE LLC
Reel/Frame 062296/0464 →
Continuity (1)
Related Publication 20240211412A1 · Jun 27, 2024
References Cited (27)
US 9218133B2 · Starr · 2015 [cited by applicant]
US 9679646B2 · Ishitobi et al. · 2017 [cited by applicant]
US 9734169B2 · Redlich et al. · 2017 [cited by applicant]
US 9904603B2 · Mutalik et al. · 2018 [cited by applicant]
US 10521230B2 · DeHon · 2019 [cited by applicant]
US 10789003B1 · Sun et al. · 2020 [cited by applicant]
US 10846199B2 · Mola et al. · 2020 [cited by applicant]
US 11188639B2 · LeMay et al. · 2021 [cited by applicant]
US 20110153944A1 · Kursawe · 2011 [cited by examiner]
US 20110173676A1 · Peckover · 2011 [cited by examiner]
US 20140006355A1 · Kirihata · 2014 [cited by applicant]
US 20190138411A1 · Lesartre · 2019 [cited by examiner]
US 20190272159A1 · Pizlo · 2019 [cited by examiner]
US 20200125770A1 · LeMay et al. · 2020 [cited by applicant]
US 20210149825A1 · Durham · 2021 [cited by examiner]
US 20220121447A1 · Basak · 2022 [cited by examiner]
US 20230412648A1 · Noon · 2023 [cited by examiner]
CN 115391235A · 2022 [cited by applicant]
WO 2017136090A1 · 2017 [cited by applicant]
WO WO2019012288A1 · 2019 [cited by examiner]
WO WO2019172987A1 · 2019 [cited by examiner]
T. Palit, J. Firose Moon, F. Monrose and M. Polychronakis, “DynPTA: Combining Static and Dynamic Analysis for Practical Selective Data Protection,” 2021 IEEE Symposium on Security and Privacy (SP), San Francisco, CA, US… [cited by examiner]
W. Shi, J. B. Fryman, G. Gu, H. . -H. S. Lee, Y. Zhang and J. Yang, “InfoShield: a security architecture for protecting information usage in memory,” The Twelfth International Symposium on High-Performance Computer Arch… [cited by examiner]
L. Semeria and G. De Micheli, “Resolution, optimization, and encoding of pointer variables for the behavioral synthesis from C,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20,… [cited by examiner]
M. T. I. Ziad, M. A. Arroyo, E. Manzhosov, V. P. Kemerlis and S. Sethumadhavan, “EPI: Efficient Pointer Integrity For Securing Embedded Systems,” 2021 International Symposium on Secure and Private Execution Environment … [cited by examiner]
J. Roney, T. Appel, P. Pinisetti and J. Mickens, “Identifying Valuable Pointers in Heap Data,” 2021 IEEE Security and Privacy Workshops (SPW), San Francisco, CA, USA, 2021, pp. 373-382. [cited by examiner]
Exnteded European Search Report for European Patent Application No. 23174789.0 dated Oct. 17, 2023. 9 pages. [cited by applicant]