Independently-addressable high power surface-emitting laser array with tight-pitch packing
A semiconductor surface-emitting laser array can be provided with a group of independently addressable light-emitting pixels arranged in at least two rows and in a linear array on a common substrate chip and including a common cathode and a dedicated channel associated with an address trace line for each pixel. An aggregate linear pitch can be achieved between pixels of the at least two rows along the linear array in a cross process direction that is less than the size of a pixel. The semiconductor laser array can include more than one common substrate chip tiled and stitched together in a staggered arrangement to provide an at least 11-inch wide, 1200 dpi imager with timing delays associated with each of the more than one common substrate chip in the staggered arrangement.
1 . A semiconductor surface-emitting laser array, comprising:
a plurality of independently addressable light-emitting pixels arranged in at least two rows offset relative to each other to form an interdigitated linear array of light emitters on a common substrate chip and including a common cathode and a dedicated channel associated with an address trace line for each pixel, wherein the interdigitated linear array is configured in a tight pitch arrangement wherein an aggregate linear pitch between pixels of the at least two rows along the linear array in a cross process direction is less than the size of a pixel, wherein the aggregate linear pitch between the pixels further comprises a cross spacing between adjacent cross process direction lasers regardless of a position of the lasers in a process direction; and
a submount comprising a three-dimensional mechanical body with a built-in heat sink for dissipating heat generated by the semiconductor surface-emitting laser array, wherein the submount further comprises integrated slots dimensioned and positioned to receive driver chips or electrical interposers for electrical connection to cathode and anode contacts of the semiconductor surface-emitting laser array, the submount further comprising mounting holes for alignment and attachment of optical elements comprising optics mounts, and wherein the submount is configured to support and align the semiconductor surface-emitting laser array, the driver chips or electrical interposers, and the optical elements in a mechanically integrated and thermally managed structure aligned with the address trace line.
2 . The semiconductor laser array of claim 1 , wherein the submount further comprises a heat pipe.
3 . The semiconductor laser array of claim 1 , wherein address trace lines associated with each of the plurality of independently addressable pixels for each of the at least two rows are fabricated to be at no more than a 22 micrometer aggregate linear pitch.
4 . The semiconductor laser array of claim 3 , wherein the address trace lines are fabricated at a width that allows lowered sheet resistance and trace voltage drop below 50% of the voltage drop across the activated pixel at a lasing threshold current.
5 . The semiconductor laser array of claim 1 , further comprising an electrical contact pad associated with each address trace line for each independently addressable semiconductor laser, wherein each electrical contact pad is configured to accept wire bonding and wherein the each electrical contact pad comprises a size that allows for the wire bonding, and wherein the each address trace line is of a width that allows for a low sheet resistance and a negligible voltage drop when electrified with a signal during an operation of the semiconductor laser array.
6 . The semiconductor laser array of claim 4 , wherein the plurality of independently addressable surface emitting lasers are arranged along the at least two rows with one set of address lines coming in from a top of the common substrate chip and are connecting to a first row of independently addressable surface emitting lasers and another set of address lines coming in from the bottom of the common substrate chip and are connecting to a second row of independently addressable surface emitting lasers.
7 . The semiconductor laser array of claim 6 , further comprising a driver circuit attached to each of the top row and bottom row of by the wire bonding to the electrical pads associated with each of the top row and bottom row.
8 . The semiconductor laser array of claim 6 , wherein a first row and a second row of the at least two rows are offset with respect to each other to form the interdigitated linear array of light emitters.
9 . The semiconductor laser array of claim 5 , wherein electrical contact pads are positioned in a staggered arrangement to enable wire bonding and also enable the contact pads to fit within a space between the address trace lines.
10 . The semiconductor laser array of claim 1 , wherein the common substrate chip contains at least 1000 independently addressable surface emitting lasers.
11 . The semiconductor laser array of claim 10 , further comprising more than one common substrate chip tiled and stitched together side-by-side to provide an at least 11-inch wide, 1200 dpi imager.
12 . The semiconductor laser array of claim 10 , further comprising more than one common substrate chip tiled and stitched together in a staggered arrangement to provide an at least 11-inch wide, 1200 dpi imager with timing delays associated with each of the more than one common substrate chip in the staggered arrangement.
13 . The semiconductor laser array of claim 1 , wherein each address trace line associated with each channel for each of the plurality of independently addressable surface emitting lasers further comprises more than one aperture operable in common with one another, the more than one aperture comprising multiple electrically-connected apertures.
14 . The semiconductor laser array of claim 13 , wherein the more than one aperture operable in common with one another is a double-aperture pixel.
15 . The semiconductor laser array of claim 13 , wherein the plurality of independently addressable surface emitting lasers are arranged along four interdigitated rows from top to bottom with one set of address lines coming in from a top of the common substrate chip and are connecting to a first row and second row of independently addressable surface emitting lasers and another set of address lines are coming in from the bottom of the common substrate chip and are connecting to a third and fourth row of independently addressable surface emitting lasers.
16 . The semiconductor laser array of claim 15 , further comprising a driver circuit attached to each of the top row and bottom row of by the wire bonding to the electrical pads associated with each of the top row and bottom row.
17 . The semiconductor laser array of claim 16 , wherein each of rows two, three and four are operable with a different time delay with respect the first row by operation of the driver circuits attached to each of the rows.
18 . The semiconductor laser array of claim 16 , wherein the time delay for each row is based on the distance of row two from row one, row three from row two, and row four from row three.
19 . The semiconductor laser array of claim 1 , wherein the submount comprises a 3D mechanical block including at least one liquid cooled channel therein among a plurality of embedded cooling fluid channels for flowing cooling fluids and configured to mount the common substrate chip including the plurality of independently addressable surface emitting lasers arranged in a linear array thereon and operate to control temperature of the independently addressable surface emitting lasers during their operation and wherein the 3D mechanical block functions as a cathode electrical contact for the semiconductor laser array, wherein a laser chip comprises the semiconductor laser array.
20 . The semiconductor laser array of claim 1 , wherein the plurality of independently addressable surface emitting lasers are arranged along six interdigitated rows from top to bottom along a process direction with one set of address lines coming in from a top of the common substrate chip and are connecting to the first through third rows of independently addressable surface emitting lasers and another set of address lines are coming in from the bottom of the common substrate chip and are connecting to the fourth through sixth rows of independently addressable surface emitting lasers.
21 . The semiconductor laser array of claim 20 , wherein electrical contact pads associated with each laser of the surface emitting lasers are fabricated in a staggered arrangement on each side of the electrical contact pads to enable wire bonding and also enable the contact pads to fit within available space between the address trace lines.
22 . The semiconductor laser array of claim 20 , further comprising each row operated with timing delays to accommodate a position of each row with respect to the first row, wherein imperfections in alignment are accommodated by performing calibrations to adjust relative timing delays for each laser chip among the semiconductor laser array.
23 . The semiconductor laser array of claim 20 , wherein each address trace line associated with each channel for each of the plurality of independently addressable surface emitting lasers further comprises more than one aperture operable in common with one another.
24 . The semiconductor laser array of claim 23 , wherein each address trace line associated with teach channel for each of the plurality of independently addressable surface emitting lasers is formed around adjacent pixels.
25 . The semiconductor laser array of claim 13 , wherein the more than one aperture operable in common is a multiple-aperture pixel.
26 . A semiconductor surface-emitting laser array, comprising:
a plurality of independently addressable pixels arranged in an interdigitated linear array on a common substrate chip and including a dedicated channel associated with an address trace line for each pixel, wherein the interdigitated linear array is configured in a tight pitch arrangement;
at least one laser aperture associated with each independently addressable pixel, wherein each of the at least one aperture is configured to fit within a pitch of each address trace line associated with each channel for each of the plurality of independently addressable pixels, wherein the squeezed of the shape is along a direction of the linear array to fit within available space of the pitch or the elongated is in a direction of an address line;
an electrical contact pad associated with each address trace line for each independently addressable pixel, wherein each electrical contact pad is configured to accept wire bonding;
wherein the plurality of independently addressable pixels is arranged along at least two rows with one set of address lines coming in from a top of the common substrate chip and are connecting to a first row of independently addressable pixels and another set of address lines coming in from the bottom of the common substrate chip and are connected to a second row of independently addressable pixels; and
a submount with a built-in heat sink for dissipating heat generated by the semiconductor surface-emitting laser array, the submount comprising a three-dimensional mechanical body, the submount comprising integrated slots dimensioned and positioned to receive driver chips or electrical interposers for electrical connection to cathode and anode contacts of the semiconductor surface-emitting laser array, wherein the submount comprises mounting holes for alignment and attachment of optical elements comprising optics mounts and wherein the submount is configured to support and align the semiconductor surface-emitting laser array, the driver chips or electrical interposers, and the optical elements in a mechanically integrated and thermally managed structure aligned with the each address trace line.
27 . The semiconductor laser array of claim 26 , further comprising a driver circuit attached to each of the top row and bottom row by wire bonding to the electrical pads associated with each of the top row and bottom row.
28 . The semiconductor laser array of claim 26 , wherein the first and second rows are offset with respect to each other to form an interdigitated linear array of light emitters.
29 . The semiconductor laser array of claim 26 , wherein electrical contact pads are positioned in a staggered arrangement to enable wire bonding and also enable the contact pads to fit within space between the address trace lines.
30 . The semiconductor laser array of claim 26 , wherein the common substrate chip contains at least 1000 independently addressable surface emitting lasers thereon.
31 . The semiconductor laser array of claim 30 , further comprising more than one common substrate chip tiled and stitched together side-by-side to provide an at least 11-inch wide, 1200 dpi imager.
32 . The semiconductor laser array of claim 30 , further comprising more than one common substrate chip tiled and stitched together in a staggered arrangement to provide an at least 11-inch wide, 1200 dpi imager with timing delays associated with each of the more than one common substrate chip in the staggered arrangement.
33 . The semiconductor laser array of claim 26 wherein the plurality of independently addressable pixels are semiconductor lasers arranged along four interdigitated rows from top to bottom with one set of address lines coming in from a top of the common substrate chip and are connecting to a first row and second row of independently addressable surface emitting lasers and another set of address lines are coming in from the bottom of the common substrate chip and are connecting to a third and fourth row of independently addressable surface emitting lasers.
34 . The semiconductor laser array of claim 33 , further comprising a driver circuit attached to each of the top row and bottom row of by the wire bonding to the electrical pads associated with each of the top row and bottom row.
35 . The semiconductor laser array of claim 34 , wherein each of rows two, three and four are operable with a different time delay with respect the first row by operation of the driver circuits attached to each of the rows.
36 . The semiconductor laser array of claim 34 , wherein the time delay for each row is based on the distance of row two from row one, row three from row two, and row four from row three.