IP Library Granted Patent US 12,572,473
Granted Patent B1
US 12,572,473 · App. 18/926,266 · Granted Mar 10, 2026

Prefetch circuitry with compression for demoted entries

Inventors: Jeremie S. Kim (Pittsburgh, PA); Stephen G. Meier (Los Altos, CA); Tyler J. Huberty (Sunnyvale, CA)
Assignee: Apple Inc.
G06F12/0862G06F2212/401
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Quick Facts
Patent No.
US 12,572,473
App. No.
18/926,266
Granted
Mar 10, 2026
Kind
B1
Abstract

Disclosed techniques related to compressed storage for access maps demoted from a prefetch table. In some embodiments, prefetch circuitry stores access map data based on address information corresponding to memory accesses, where a given access map of a plurality of stored access maps records categories of prior accesses to different offsets in a defined address region. The prefetch circuit may generate, based on the access map data and stored access patterns, one or more prefetch requests to prefetch data to a cache. Compressed map storage circuitry may store first data from a first access map, where the first data is a proper subset of data stored in the first access map prior to demotion of the first access map from the prefetch table. At least a portion of the first data may be a compressed version of data from the first access map.

Claims (87)

1 . An apparatus, comprising:

memory circuitry; and

a processor configured to execute program instructions that access data in the memory circuitry, wherein the processor includes:

data cache circuitry configured to cache data from the memory circuitry;

prefetch circuitry configured to:

store access map data based on address information corresponding to memory accesses, wherein a given access map of a plurality of stored access maps records categories of prior accesses to different offsets in a defined address region; and

generate, based on the access map data and stored access patterns, one or more prefetch requests to prefetch data from the memory circuitry to the data cache circuitry;

determine replacement information for stored access maps; and

select a first access map for removal from the prefetch circuitry based on the replacement information;

compressed map storage circuitry configured to store first data from the first access map, wherein the first data is a subset of data stored in the first access map, that is less than the entirety of the data prior to the removal and wherein at least a portion of the first data is a compressed version of data from the first access map; and

control circuitry configured to, in response to an access to a memory address that matches the stored first data in the compressed map storage circuitry, allocate an access map in the prefetch circuitry with promoted access map information generated based on the stored first data.

2 . An apparatus, comprising:

prefetch circuitry configured to:

store access map data based on address information corresponding to memory accesses, wherein a given access map of a plurality of stored access maps records categories of prior accesses to different offsets in a defined address region; and

generate, based on the access map data and stored access patterns, one or more prefetch requests to prefetch data to a cache;

determine replacement information for stored access maps; and

select a first access map for removal from the prefetch circuitry based on the replacement information;

compressed map storage circuitry configured to store first data from the first access map, wherein the first data is a subset of data stored in the first access map, that is less than the entirety of the data prior to the removal and wherein at least a portion of the first data is a compressed version of data from the first access map; and

control circuitry configured to, in response to an access to a memory address that matches the stored first data in the compressed map storage circuitry, allocate an access map in the prefetch circuitry with promoted access map information generated based on the stored first data.

3 . The apparatus of claim 2 , wherein the first data further includes:

granularity information that indicates a distance between offsets for the first access map; and

quality factor information that indicates accuracy of prefetches that have been performed based on the first access map.

4 . The apparatus of claim 3 , wherein the promoted access map information includes:

a granularity for the allocated access map based on the granularity information in the first data;

starting access map categories for the allocated access map based on the compressed version of the data from the first access map; and

quality factor information based on quality factor information in the first data.

5 . The apparatus of claim 2 , wherein:

the prefetch circuitry supports a first number of categories of prior accesses represented using a first number of bits; and

the compressed version of the data from the first access map supports a second, smaller number of categories of prior accesses represented using a second, smaller number of bits.

6 . The apparatus of claim 5 , wherein:

the data from the first access map supports distinct categories for:

launched prefetches to a cache level; and

prefetches that were subsequently hit by a demand access;

the compressed version of the data supports a single category for launched prefetches to the cache level and prefetches that were subsequently hit by a demand access;

the data from the first access map supports distinct categories for:

pending prefetches; and

no access; and

the compressed version of the data supports a single category for pending prefetches and no access.

7 . The apparatus of claim 2 , wherein the compressed map storage circuitry is configured to determine hits and misses in its entries based on at least a portion of virtual addresses for demand accesses.

8 . The apparatus of claim 2 , wherein the compressed map storage circuitry includes:

a first content-addressable memory configured to determine whether there is a hit in the compressed map storage circuitry for a miss in the prefetch circuitry;

a second content-addressable memory configured to invalidate an entry in the compressed map storage circuitry based on a granularity change for an overlapping access map in the prefetch circuitry; and

a third content-addressable memory configured to invalidate an entry in the compressed map storage circuitry when chaining for an access map in the prefetch circuitry overwrites a portion of the access map that overlaps with the entry.

9 . The apparatus of claim 2 , wherein the compressed map storage circuitry is configured to:

for an access map that meets a threshold granularity, reduce the granularity for storage in the first data and clear the access map for storage, wherein granularity indicates a distance between offsets for a given access map; and

utilize a default starting access map and the reduced granularity in conjunction with promotion to the prefetch circuitry.

10 . The apparatus of claim 2 , wherein the compressed map storage circuitry is configured not to store granularity up-switch metadata from the first access map used to determine when to up-switch granularity to increase distance between offsets in a given access map.

11 . The apparatus of claim 2 , wherein the control circuitry is further configured to:

adjust a counter in a first direction in response to a given access map falling below a threshold position in a least-recently-used scheme;

adjust the counter in an opposite direction in response to a demand access that touches the access map when the access map is not below the threshold position; and

prevent up-switch of the access map above a threshold granularity between offsets in the access map based on the counter having a value past a counter threshold in the first direction.

12 . The apparatus of claim 2 , wherein the control circuitry is configured to allocate the access map in the prefetch circuitry with the promoted access map information, at a position in a least-recently-used value that is not a most-recently-used position.

13 . The apparatus of claim 2 , wherein the apparatus is a computing device that further includes:

a processor that includes the prefetch circuitry, the compressed map storage circuitry, and the control circuitry;

a display; and

network interface circuitry.

14 . A method, comprising:

storing, by a computing device in a prefetch table, access map data based on address information corresponding to memory accesses, wherein a given access map of a plurality of stored access maps records categories of prior accesses to different offsets in a defined address region;

generating, by the computing device based on the access map data and stored access patterns, one or more prefetch requests to prefetch data to a cache;

determining, by the computing device, replacement information for stored access maps;

selecting, by the computing device, a first access map for removal from the prefetch table based on the replacement information;

storing, by the computing device in compressed map storage, first data from the first access map, wherein the first data is a subset of data stored in the first access map, that is less than the entirety of the data prior to the removal and wherein at least a portion of the first data is a compressed version of data from the first access map; and

allocating, by the computing device in response to an access to a memory address that matches the stored first data in the compressed map storage, an access map in the prefetch table with promoted access map information generated based on the stored first data.

15 . The method of claim 14 , wherein the first data further includes:

granularity information that indicates a distance between offsets for the first access map; and

quality factor information that indicates accuracy of prefetches that have been performed based on the first access map.

16 . The method of claim 15 , wherein the promoted access map information includes:

a granularity for the allocated access map based on the granularity information in the first data;

starting access map categories for the allocated access map based on the compression version of the data from the first access map; and

quality factor information based on quality factor information in the first data.

17 . The method of claim 14 , wherein:

the prefetch table supports a first number of categories of prior accesses represented using a first number of bits; and

the compressed version of the data from the first access map supports a second, smaller number of categories of prior accesses represented using a second, smaller number of bits.

18 . The method of claim 17 , wherein:

the data from the first access map supports distinct categories for:

launched prefetches to a cache level; and

prefetches that were subsequently hit by a demand access;

the compressed version of the data supports a single category for launched prefetches to the cache level and prefetches that were subsequently hit by a demand access;

the data from the first access map supports distinct categories for:

pending prefetches; and

no access; and

the compressed version of the data supports a single category for pending prefetches and no access.

19 . The method of claim 14 , further comprising:

determining, by the computing device, hits and misses in its entries based on at least a portion of virtual addresses for demand accesses.

20 . The method of claim 14 , further comprising:

for an access map that meets a threshold granularity, the computing device reducing the granularity for storage in the first data and clear the access map for storage, where granularity indicates a distance between offsets for a given access map; and

utilizing a default starting access map and the reduced granularity in conjunction with promotion to the prefetch table.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2024
From: KIM, JEREMIE S.; MEIER, STEPHEN G.; HUBERTY, TYLER J.
To: APPLE INC.
Reel/Frame 069014/0417 →
Continuity (1)
Provisional Application 63692910 · Sep 10, 2024
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