Pattern match prefetcher with supplemental program-counter-based learning
Disclosed techniques relate to supplemental PC-based learning for a pattern-based prefetcher. In some embodiments, prefetch circuitry is configured to store access map data based on address information corresponding to memory accesses and generate, based on the access map data and stored access patterns, one or more prefetch requests to prefetch data to a cache. In some embodiments, supplemental access tracking circuitry is configured to store initial access tracking information for offsets corresponding to a first access map evicted from the prefetch circuitry, store program counter information associated with an initial memory access that touched the first access map, update the access tracking information, based on one or more additional access maps evicted from the prefetch circuitry that match the stored program counter information, and generate, in response to a hit and based on the updated access tracking information, a starting access map for allocation in the prefetch circuitry.
1 . A method, comprising:
storing, by a computing system in a prefetch table, access map data based on address information corresponding to memory accesses, wherein a given access map of a plurality of stored access maps records categories of prior accesses to different offsets in a defined address region;
generating, by the computing system based on the access map data and stored access patterns, one or more prefetch requests to prefetch data to a cache;
storing, by the computing system, initial access tracking information for offsets corresponding to a first access map evicted from the prefetch table;
storing, by the computing system, program counter information associated with an initial memory access that touched the first access map;
updating, by the computing system, the access tracking information, based on one or more additional access maps evicted from the prefetch table that match the stored program counter information;
detecting, by the computing system, a hit for the updated access tracking information based on comparison of the stored program counter information and program counter information for a subsequent memory access; and
generating, by the computing system in response to the hit and based on the updated access tracking information, a starting access map for allocation in the prefetch table.
2 . The method of claim 1 , wherein:
the initial access tracking information includes respective counter values for different offsets in the defined address region; and
the updating includes adjusting one or more of the counter values based on the one or more additional evicted access maps.
3 . The method of claim 2 , wherein the generating includes determining starting symbols at different offsets based on corresponding counter values of the access tracking information.
4 . The method of claim 1 , wherein the generating includes aligning the first access map with the offset of the initial memory access that touched the first access map.
5 . The method of claim 1 , wherein:
the prefetch table supports multiple different granularities corresponding to distance between offsets in a given access map; and
the method further comprises storing granularity information that indicates a granularity of the first access map.
6 . The method of claim 5 , further comprising:
in response to a threshold number of mismatches between the stored granularity information and granularities of subsequently evicted access maps, updating the stored granularity information to match the granularity of the subsequently evicted access maps.
7 . The method of claim 5 , further comprising:
restoring the stored granularity for the starting access map.
8 . The method of claim 1 , wherein the program counter information is a hashed program counter.
9 . The method of claim 1 , wherein the starting access map is different than a default starting access map that is a bi-directional density pattern.
10 . An apparatus, comprising:
memory circuitry; and
a processor configured to execute program instructions that access data in the memory circuitry, wherein the processor includes:
data cache circuitry configured to cache data from the memory circuitry;
prefetch circuitry configured to:
store access map data based on address information corresponding to memory accesses, wherein a given access map of a plurality of stored access maps records categories of prior accesses to different offsets in a defined address region; and
generate, based on the access map data and stored access patterns, one or more prefetch requests to prefetch data from the memory circuitry to the data cache circuitry; and
supplemental access tracking circuitry configured to:
store initial access tracking information for offsets corresponding to a first access map evicted from the prefetch circuitry;
store program counter information associated with an initial memory access that touched the first access map;
update the access tracking information, based on one or more additional access maps evicted from the prefetch circuitry that match the stored program counter information;
detect a hit for the updated access tracking information based on comparison of the stored program counter information and program counter information for a subsequent memory access; and
generate, in response to the hit and based on the updated access tracking information, a starting access map for allocation in the prefetch circuitry.
11 . An apparatus, comprising:
prefetch circuitry configured to:
store access map data based on address information corresponding to memory accesses, wherein a given access map of a plurality of stored access maps records categories of prior accesses to different offsets in a defined address region; and
generate, based on the access map data and stored access patterns, one or more prefetch requests to prefetch data to a cache; and
supplemental access tracking circuitry configured to:
store initial access tracking information for offsets corresponding to a first access map evicted from the prefetch circuitry;
store program counter information associated with an initial memory access that touched the first access map;
update the access tracking information, based on one or more additional access maps evicted from the prefetch circuitry that match the stored program counter information;
detect a hit for the updated access tracking information based on comparison of the stored program counter information and program counter information for a subsequent memory access; and
generate, in response to the hit and based on the updated access tracking information, a starting access map for allocation in the prefetch circuitry.
12 . The apparatus of claim 11 , wherein:
the initial access tracking information includes respective counter values for different offsets in the defined address region; and
the update to the access tracking information includes adjusting one or more of the counter values based on the one or more additional evicted access maps.
13 . The apparatus of claim 12 , wherein, to generate the starting access map, the supplemental access tracking circuitry is configured to determine starting symbols at different offsets based on corresponding counter values of the access tracking information.
14 . The apparatus of claim 11 , wherein, to generate the initial access tracking information, the supplemental access tracking circuitry is further configured to align the first access map with the offset of the initial memory access that touched the first access map.
15 . The apparatus of claim 11 , wherein:
the prefetch circuitry supports multiple different granularities corresponding to distance between offsets in a given access map; and
the supplemental access tracking circuitry is further configured to store granularity information that indicates a granularity of the first access map.
16 . The apparatus of claim 15 , wherein:
in response to a threshold number of mismatches between the stored granularity information and granularities of subsequently evicted access maps, the supplemental access tracking circuitry is configured to update the stored granularity information to match the granularity of the subsequently evicted access maps.
17 . The apparatus of claim 15 , wherein the supplemental access tracking circuitry is configured to restore the stored granularity for the starting access map.
18 . The apparatus of claim 11 , wherein the program counter information is a hashed program counter.
19 . The apparatus of claim 11 , wherein the starting access map is different than a default starting access map that the prefetch circuitry is configured to use if there is not a hit in the supplemental access tracking circuitry.
20 . The apparatus of claim 11 , wherein the apparatus is a computing device that further includes:
a processor that includes the prefetch circuitry and the supplemental access tracking circuitry;
a display; and
network interface circuitry.