Multi-bus replicator using RF serializer/deserializer for chip-to-chip interconnect
Multiple examples are disclosed of a multi-bus replicator using RF SerDes components for a chip-to-chip interconnect. In one example, a multi-bus replicator comprises an initiator write bus replication unit to receive write commands and write data from a plurality of write buses and to transmit the write commands and the write data using one or more RF SerDes transmitters; and a target write bus replication unit to receive the write commands and the write data from the RF SerDes transmitters and to provide the write commands and the write data on a plurality of write buses.
1 . A multi-bus replicator, comprising:
an initiator write bus replication unit to receive write commands and write data from a first plurality of write buses and to transmit the write commands and the write data using one or more RF SerDes transmitters, each of the first plurality of write buses following a different bus protocol; and
a target write bus replication unit to receive the write commands and the write data from the RF SerDes transmitters and to replicate the write commands and the write data on a second plurality of write buses on a cycle-by-cycle basis, wherein the second plurality of write buses replicates the first plurality of write buses.
2 . The multi-bus replicator of claim 1 , wherein the first plurality of write buses and the second plurality of write buses each comprises two or more of an Advanced Peripheral Bus, a non-cacheable AXI bus, a cacheable AXI bus, a neural processing unit bus, a graphics processing unit bus, and a media processor bus.
3 . The multi-bus replicator of claim 1 , comprising:
an initiator read bus replication unit to receive read commands from a first plurality of read buses and to transmit the read commands using one or more RF SerDes transmitters; and
a target read bus replication unit to receive the read commands and to provide the read commands on a second plurality of read buses, wherein the second plurality of read buses replicates the first plurality of read buses.
4 . The multi-bus replicator of claim 3 ,
wherein the target read bus replication unit is further configured to receive read data from a distributed memory pool in response to the read commands and to transmit the read data using one or more SerDes transmitters.
5 . The multi-bus replicator of claim 4 , wherein the initiator read bus replication unit is further configured to receive the read data from the target read bus replication unit.
6 . A multi-bus replicator, comprising:
an initiator read bus replication unit to receive read commands from a first plurality of read buses and to transmit the read commands using one or more RF SerDes transmitters, each of the first plurality of read buses following a different bus protocol; and
a target read bus replication unit to receive the read commands and to replicate the read commands on a second plurality of read buses on a cycle-by-cycle basis, wherein the second plurality of read buses replicates the first plurality of read buses.
7 . The multi-bus replicator of claim 6 , wherein the first plurality of read buses and the second plurality of read buses each comprises two or more of an Advanced Peripheral Bus, a non-cacheable AXI bus, a cacheable AXI bus, a neural processing unit bus, a graphics processing unit bus, and a media processor bus.
8 . The multi-bus replicator of claim 6 ,
wherein the target read bus replication unit is further configured to receive read data from a distributed memory pool in response to the read commands and to transmit the read data using one or more RF SerDes transmitters.
9 . The multi-bus replicator of claim 8 , wherein the initiator read bus replication unit is further configured to receive the read data from the target read bus replication unit.
10 . A multi-bus replicator, comprising:
an initiator write bus replication unit coupled to a first plurality of buses, each of the first plurality of buses following a different bus protocol;
a target write bus replication unit coupled to a second plurality of buses, wherein the second plurality of buses replicates the first plurality of buses;
an initiator read bus replication unit coupled to the first plurality of buses; and
a target read bus replication unit coupled to the second plurality of buses;
wherein the initiator write bus replication unit and the target write bus replication unit are capable of performing write operations concurrently with the initiator read bus replication unit and the target read bus replication unit performing read operations.
11 . The multi-bus replicator of claim 10 , comprising:
an RF SerDes transmitter coupled to the initiator write bus replication unit; and
an RF SerDes receiver coupled to the target write bus replication unit;
wherein the RF SerDes transmitter transmits to the RF SerDes receiver over a physical link.
12 . The multi-bus replicator of claim 10 , comprising:
a first RF SerDes transmitter coupled to the initiator read bus replication unit;
a first RF SerDes receiver coupled to the initiator read bus replication unit;
a second RF SerDes transmitter coupled to the target read bus replication unit; and
a second RF SerDes receiver coupled to the target read bus replication unit;
wherein the first RF SerDes transmitter transmits to the second RF SerDes receiver over a physical link and the second RF SerDes transmitter transmits to the first SerDes receiver over the physical link.
13 . A method comprising:
receiving a write command and write data from one of a first plurality of write buses, each of the first plurality of write buses following a different bus protocol;
sending, by a RF SerDes transmitter, the write command and the write data;
receiving, by a RF SerDes receiver, the write command and the write data; and
replicating the write command and the write data on one of a second plurality of write buses on a cycle-by-cycle basis, wherein the second plurality of write buses replicates the first plurality of write buses.
14 . The method of claim 13 , wherein the first plurality of write buses comprises two or more of an Advanced Peripheral Bus, a non-cacheable AXI bus, a cacheable AXI bus, a neural processing unit bus, a graphics processing unit bus, and a media processor bus.
15 . The method of claim 14 , wherein the second plurality of write buses comprises two or more of an Advanced Peripheral Bus, a non-cacheable AXI bus, a cacheable AXI bus, a neural processing unit bus, a graphics processing unit bus, and a media processor bus.
16 . A method comprising:
receiving a read command from a processor over one of a first plurality of read buses each of the first plurality of read buses following a different bus protocol;
sending, by a RF SerDes transmitter, the read command;
receiving, by a RF SerDes receiver, the read command; and
replicating the read command to a memory unit over one of a second plurality of read buses on a cycle-by-cycle basis, wherein the second plurality of read buses replicates the first plurality of read buses.
17 . The method of claim 16 , wherein the first plurality of read buses comprises two of an Advanced Peripheral Bus, a non-cacheable AXI bus, a cacheable AXI bus, a neural processing unit bus, a graphics processing unit bus, and a media processor bus.
18 . The method of claim 17 , wherein the second plurality of read buses comprises two of an Advanced Peripheral Bus, a non-cacheable AXI bus, a cacheable AXI bus, a neural processing unit bus, a graphics processing unit bus, and a media processor bus.
19 . The method of claim 16 , comprising:
receiving read data from the memory unit over the one of a second plurality of read buses.
20 . The method of claim 19 , comprising:
sending, by a RF SerDes transmitter, the read data;
receiving, by a RF SerDes receiver, the read data; and
sending the read data to the processor over the one of a first plurality of read buses.