DRAM layout for logical-to-physical (L2P) address indirection table (AIT)
This application is directed to compressing a logical-to-physical address indirection table in a memory system of an electronic device. The electronic device identifies an address block including a plurality of physical addresses that corresponds to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device further determines that a first physical address is associated with a first word having a first word location in the address block, and extracts the first word from the first word location in the address block. Based on the first word location, the electronic device determines a first bit location in a supplemental word that is distinct from the first word. The electronic device extracts at least a first bit from the first bit location of the supplemental word, and generates the first physical address based on the first word and the first bit.
1 . A method implemented at an electronic device, the method comprising:
identifying an address block including a plurality of physical addresses that corresponds to an ordered sequence of logical addresses, each logical address corresponding to a distinct physical address;
determining that a first physical address is associated with a first word having a first word location in the address block;
extracting the first word from the first word location in the address block;
based on the first word location, determining a first bit location in a supplemental word that is distinct from the first word, the first bit location in the supplemental word associated with the first word location in the address block;
extracting at least a first bit from the first bit location of the supplemental word; and
generating the first physical address based on the first word and the first bit;
wherein the address block includes a plurality of non-overlapping portions, and each respective portion of the address block includes a respective word choice configured to provide the supplemental word having bits to be combined with remaining address words in the respective portion of the address block.
2 . The method of claim 1 , wherein the first bit location is measured successively from a start bit of the supplemental word and represented by a first integer number, and the first word location is measured successively from a start word of the address block and represented by a second integer number, the first integer number being determined from the second integer number.
3 . The method of claim 1 , further comprising:
selecting the supplemental word from a plurality of word choices located at a plurality of distinct known word locations in the address block.
4 . The method of claim 3 , wherein the plurality of word choices include two word choices located at two distinct word locations in the address block, wherein selecting the supplemental word further comprises:
applying a bitwise logic operation on a set of first predefined bits of a binary representation of the first word location to determine a set of first corresponding bits of a binary representation of one of the two distinct word locations.
5 . The method of claim 4 , wherein bit locations of each first predefined bit of the binary representation of the first word location and a corresponding first bit of the binary representation of one of the two distinct word locations matches one another.
6 . The method of claim 4 , wherein the bitwise logic operation includes an OR operation or an AND operation.
7 . The method of claim 4 , wherein binary representations of the two distinct word locations of the two word choices differ by one bit.
8 . The method of claim 3 , wherein the plurality of word choices include two word choices located at two distinct word locations in the address block, wherein selecting the supplemental word further comprises:
extracting a second predefined bit of a binary representation of the first word location; and
determining a corresponding second bit of a binary representation of a supplemental word location of the supplemental word based on the second predefined bit of the binary representation of the first word location, wherein the supplemental word is selected from the two word choices based on the corresponding second bit of the supplemental word location.
9 . The method of claim 1 , wherein:
the electronic device includes a memory controller and a volatile memory, and the volatile memory stores a logical-to-physical (L2P) address indirection table (AIT) including the address block;
a portion of the address block includes both of the first word and the supplemental word, the portion less than all of the address block; and
the method further comprising, at the memory controller:
obtaining a request for the first physical address; and
in response to the request, extracting the portion of the address block from the volatile memory.
10 . The method of claim 9 , wherein the address block includes 128 bytes, and the portion of the address block includes 64 bytes.
11 . The method of claim 1 , wherein the address block includes 128 bytes and corresponds to 31 physical addresses, and each physical address has 33 bits.
12 . An electronic device, comprising:
one or more processors; and
memory storing one or more programs for execution by the one or more processors, the one or more programs including instructions for:
identifying an address block including a plurality of physical addresses that corresponds to an ordered sequence of logical addresses, each logical address corresponding to a distinct physical address;
determining that a first physical address is associated with a first word having a first word location in the address block;
extracting the first word from the first word location in the address block;
based on the first word location, determining a first bit location in a supplemental word that is distinct from the first word, the first bit location in the supplemental word being determined from the first word location in the address block;
extracting at least a first bit from the first bit location of the supplemental word; and
generating the first physical address based on the first word and the first bit;
wherein the address block includes a plurality of non-overlapping portions, and each respective portion of the address block includes a respective word choice configured to provide the supplemental word having bits to be combined with remaining address words in the respective portion of the address block.
13 . The electronic device of claim 12 , wherein for each non-overlapping portion, the respective word choice includes a first set of bits that are supplemental to the remaining address words in the respective portion and a second set of leftover bits, and wherein the one or more programs further comprise instructions for:
consolidating the second set of leftover bits of each of the plurality of non-overlapping portions to provide a remaining physical address.
14 . The electronic device of claim 13 , wherein:
the electronic device includes a memory controller and a volatile memory, and the volatile memory stores an L2P AIT including the address block; and
the one or more programs further comprise instructions for, at the memory controller:
obtaining a request associated with the remaining physical address; and
in response to the request, extracting the plurality of non-overlapping portions of the address block from the volatile memory.
15 . The electronic device of claim 12 , wherein, for a first portion of the address block:
each of the remaining address words has a respective word location and corresponds to a respective bit in the supplemental word, and a respective bit location of the respective bit in the supplemental word is associated with the respective word location of the respective remaining address word in first portion of the address block according to a predefined relationship.
16 . The electronic device of claim 15 , wherein the predefined relationship applies to all of the remaining address words in the first portion of the address block.
17 . The electronic device of claim 12 , wherein:
the address block includes 128 bytes and corresponds to 31 physical addresses, and each physical address has 33 bits;
the address block is divided to two portions each of which includes 64 successive bytes, and each portion stores 15 complete physical addresses; and
each portion has a single supplemental word, and supplemental words of the two portions provide a last physical address jointly.
18 . The electronic device of claim 12 , wherein:
the address block includes 64 bytes and corresponds to 15 physical addresses, and each physical address has 34 bits;
the address block is divided to two portions each of which includes 32 successive bytes, and each portion stores 7 complete physical addresses; and
each portion has a single supplemental word, and supplemental words of the two portions provide a last physical address jointly.
19 . The electronic device of claim 12 , wherein the one or more programs further comprise instructions for:
selecting the supplemental word from a plurality of word choices located at a plurality of distinct known word locations in the address block.
20 . A non-transitory computer-readable storage medium storing one or more programs for execution by one or more processors, the one or more programs comprising instructions for:
identifying an address block including a plurality of physical addresses that corresponds to an ordered sequence of logical addresses, each logical address corresponding to a distinct physical address;
determining that a first physical address is associated with a first word having a first word location in the address block;
extracting the first word from the first word location in the address block;
based on the first word location, determining a first bit location in a supplemental word that is distinct from the first word, the first bit location in the supplemental word being determined from the first word location in the address block;
extracting at least a first bit from the first bit location of the supplemental word; and
generating the first physical address based on the first word and the first bit;
wherein the address block includes a plurality of non-overlapping portions, and each respective portion of the address block includes a respective word choice configured to provide the supplemental word having bits to be combined with remaining address words in the respective portion of the address block.