Memory device having vertical structure and memory system including the memory device
A memory device includes a first lower semiconductor layer and a second lower semiconductor layer. The first lower semiconductor layer is disposed below a first upper semiconductor layer including a first memory cell array. The first lower semiconductor layer includes a first page buffer electrically connected to the first memory cell array. The second lower semiconductor layer is disposed below a second upper semiconductor layer includes a second memory cell array and disposed adjacent to the first upper semiconductor layer in a first direction. The second lower semiconductor layer includes a first portion of a second page buffer electrically connected to the second memory cell array and being disposed adjacent to the first lower semiconductor layer in the first direction. The first lower semiconductor layer further includes a second portion of the second page buffer different from the first portion.
1 . A memory device comprising:
a first lower semiconductor layer disposed below a first upper semiconductor layer including a first memory cell array, the first lower semiconductor layer including a first page buffer unit electrically connected to the first memory cell array; and
a second lower semiconductor layer disposed below a second upper semiconductor layer including a second memory cell array and disposed adjacent to the first upper semiconductor layer in a first direction, the second lower semiconductor layer including a first portion of a second page buffer unit electrically connected to the second memory cell array and disposed adjacent to the first lower semiconductor layer in the first direction,
wherein the first lower semiconductor layer further includes a second portion of the second page buffer unit different from the first portion.
2 . The memory device of claim 1 , wherein
the first lower semiconductor layer further comprises:
a first page buffer driver disposed between the first page buffer unit and the second portion of the second page buffer unit and configured to control a cache latch of the first page buffer unit; and
a second page buffer driver disposed between the first page buffer driver and the second portion of the second page buffer unit and configured to control a cache latch of the second page buffer unit.
3 . The memory device of claim 2 , wherein the second page buffer unit includes an edge cache latch overlapping with the first upper semiconductor layer in a vertical direction, and the edge cache latch includes a plurality of cache latches disposed at an edge of the second page buffer unit to be adjacent to the second page buffer driver.
4 . The memory device of claim 3 ,
wherein the second upper semiconductor layer further includes an edge through-via portion disposed at an edge of the second upper semiconductor layer to be adjacent to the first upper semiconductor layer and including a plurality of through-vias passing through the second memory cell array to be connected to the second page buffer unit, and
wherein the second page buffer unit further includes an edge contact portion including a plurality of through-via contacts disposed to overlap with the plurality of through-vias in a vertical direction to be connected to the plurality of through-vias.
5 . The memory device of claim 4 , wherein the second page buffer unit further includes a low voltage circuit including at least one transistor configured to operate based on a low voltage, disposed between the edge cache latch and the edge contact portion, and overlapping with the first upper semiconductor layer in a vertical direction.
6 . The memory device of claim 5 , wherein the second page buffer unit further includes a high voltage circuit including at least one transistor configured to operate based on a high voltage, disposed between the low voltage circuit and the edge contact portion, and overlapping with the first upper semiconductor layer in a vertical direction.
7 . The memory device of claim 3 , wherein the second page buffer unit includes a plurality of cache latches disposed in a center of the second page buffer unit in the first direction.
8 . The memory device of claim 1 , wherein the second page buffer unit comprises:
a plurality of cache latches disposed in a center of the second page buffer unit in the first direction and overlapping with the second upper semiconductor layer in a vertical direction; and
at least one transistor configured to operate based on a low voltage and overlapping with the first upper semiconductor layer in a vertical direction.
9 . The memory device of claim 1 , wherein the second lower semiconductor layer further includes an internal peripheral circuit disposed adjacent to the first portion of the second page buffer unit in the first direction and including circuits configured to control the first memory cell array and the second memory cell array.
10 . The memory device of claim 9 , wherein the internal peripheral circuit includes at least one of a voltage generator, an error correction circuit, a scheduler, a command decoder, and an address decoder.
11 . A non-volatile memory device comprising:
a first lower semiconductor layer disposed below a first upper semiconductor layer including a first memory cell array, the first lower semiconductor layer overlapping with the first upper semiconductor layer in a vertical direction; and
a second lower semiconductor layer disposed below a second upper semiconductor layer including a second memory cell array and disposed adjacent to the first upper semiconductor layer in a first direction, the second lower semiconductor layer overlapping with the second upper semiconductor layer in a vertical direction,
wherein the first lower semiconductor layer comprises:
a first page buffer unit disposed in a second direction perpendicular to the first direction and electrically connected to the first memory cell array;
a plurality of cache latches disposed in the second direction and spaced apart from the first page buffer unit in the first direction, and disposed at an edge of a portion of a second page buffer unit electrically connected to the second memory cell array to overlap with the first upper semiconductor layer in a vertical direction; and
a first row decoder disposed adjacent to the first page buffer unit and the plurality of cache latches in the second direction and electrically connected to the first memory cell array.