Self-repairable chip for silent data corruption issues
The disclosure provides a self-repairable chip for silent data corruption (SDC) issues. The self-repairable chip is configured to detect data corruption in a plurality of processing units, identifying the defective tiles of the processing units, and repairing the defective tiles by replacing the defective tiles with redundant rows or columns. The self-repairable chip is further configured to determine whether one or more logics where the data corruption occurred must work or may work and replace the defective tiles with redundant rows or columns when the logic where the data corruption occurred may work.
1 . A device comprising:
one or more processing cores of a self repairable chip, the one or more processing cores further comprising a plurality of processing units, at least one of the plurality of processing units comprising a data processing matrix arranged in a plurality of rows and columns, the data processing matrix including at least one of a redundant column or a redundant row of processing units, the processing core configured to:
detect data corruption in the data processing matrix;
identify a row and a column of a defective tile of the data processing matrix where the data corruption occurred, the defective tile comprising at least one critical logic unit required for the self-repairable chip to function and a plurality of auxiliary logic units that are not required for the self-repairable chip to function;
determine whether a defective logic unit in the defective tile is the at least one critical logic unit or one of the plurality of auxiliary logic units; and
when the defective logic unit is one of the auxiliary logic units, replace the defective tile with one of the redundant column or the redundant row,
wherein a number of the plurality of auxiliary logic units in the defective tile is greater than a number of the at least one critical logic unit to increase the reparability of the self repairable chip, and a majority of logic units in the defective tile are the plurality of auxiliary logic units.
2 . The device of claim 1 , wherein the one or more processing cores are further configured to determine whether there is an available redundant column or redundant row and automatically replace the defective tile with the available redundant column or a redundant row.
3 . The device of claim 2 , wherein the one or more processing cores are further configured to remap a logic in the data processing matrix after replacing the defective tile with the available redundant column or row.
4 . The device of claim 3 , wherein the one or more processing cores are further configured to run testing after remapping the logic in the data processing matrix, and confirm based on the testing whether the data processing matrix is fully functional.
5 . The device of claim 1 , wherein the one or more processing cores are further configured to restore functionalities of the defective tile by blowing an e-fuse of the device.
6 . The device of claim 1 , wherein the one or more processing cores are further configured to:
execute one or more logic units in a processing tile of the data processing matrix;
determine whether the next processing tile is a tile of the redundant row or column; and
execute one or more logics in a next processing tile of the tile of the redundant row or column by bypassing the tile of the redundant row or column when the next processing tile is determined the tile of the redundant row or column.
7 . The device of claim 1 , wherein the at least one critical logic unit and the plurality of auxiliary logic units perform independently.
8 . The device of claim 1 , the device further comprising a plurality of bus and redundant bus.
9 . The device of claim 8 , the processing core further configured to replace a defective bus with the redundant bus when the defective bus is detected.
10 . The device of claim 1 , wherein the one or more processing cores are configured to repair the defective tile multiple times during a lifetime of a processing core.
11 . The device of claim 1 , wherein the one or more processing cores are configured to identify the defective tile of the data processing matrix by receiving information of the defective tile from tests for detection of silent data corruptions (SDCs).
12 . The device of claim 1 , wherein the data corruption is detected by one or more functional tests.
13 . A method for repairing data corruption on a device having a self-repairable chip, the method comprising:
detecting, by one or more processing cores comprising a plurality of processing units, the data corruption in a data processing matrix of at least one of the plurality of processing units, wherein the data processing matrix is arranged in a plurality of rows and columns and the data processing matrix includes at least one of a redundant column or a redundant row of processing units;
identifying, by one or more processing cores, a defective tile of the data processing matrix where the data corruption occurred, the defective tile comprising at least one critical logic unit required for the self-repairable chip to function and a plurality of auxiliary logic units that are not required for the self-repairable chip to function;
determining, by one or more processing cores, whether a defective logic unit in the defective tile is the at least one critical logic unit or one of the plurality of auxiliary logic units; and
replacing, by one or more processing cores, the defective tile with one of the redundant column or the redundant row when the defective logic unit is the auxiliary logic unit,
wherein a number of the plurality of auxiliary logic units in the defective tile is greater than a number of the at least one critical logic unit to increase the reparability of the self-repairable chip, and wherein a majority of logic units in the defective tile is the plurality of auxiliary logic units.
14 . The method of claim 13 , the method further comprising determining whether there is an available redundant column or redundant row, and automatically repairing the defective tile with the available redundant column or redundant row.
15 . The method of claim 13 , the method further comprising restoring functionalities of the defective tile by blowing an e-fuse of the device.
16 . The method of claim 13 , the method further comprising:
executing, by one or more processing cores, one or more logics in a processing tile of the data processing matrix;
determining, by one or more processing cores, whether the next processing tile is a tile of the redundant row or column; and
executing, by one or more processing cores, one or more logics in a next processing tile of the tile of the redundant row or column by bypassing the tile of the redundant row or column when the next processing tile is determined the tile of the redundant row or column.
17 . The method of claim 13 , wherein the at least one critical logic units and the plurality of auxiliary logic units perform independently.
18 . The method of claim 13 , wherein the device further comprises a plurality of bus and redundant bus.
19 . The method of claim 18 , the method further comprising replacing a defective bus with the redundant bus when the defective bus is detected.
20 . The method of claim 13 , wherein the replacing the defective tile with one of the redundant column or the redundant row is performed multiple times during a lifetime of a processing core.
21 . The method of claim 13 , wherein the identifying the defective tile of the data processing matrix comprises receiving information of the defective tile from tests for detection of silent data corruptions (SDCs).
22 . The method of claim 13 , wherein the data corruption is detected by one or more functional tests.