Application programming interface to allocate memory for shared virtual memory
Apparatuses, systems, and techniques to facilitate memory management. In at least one embodiment, an application programming interface is performed to cause physical memory corresponding to shared virtual memory to be designated for use by a plurality of processors.
1 . A processor comprising:
one or more circuits to perform an application programming interface (API) to receive a location of one or more physical memory addresses and cause the one or more physical memory addresses to be assigned to one or more shared virtual memory addresses to be used by a plurality of processors.
2 . The processor of claim 1 , wherein the one or more shared virtual memory addresses correspond to an address of multicast memory.
3 . The processor of claim 1 , wherein:
a first processor of the plurality of processors is to be on a first device; and
a second processor of the plurality of processors is to be on a second device.
4 . The processor of claim 1 , wherein the one or more shared virtual memory-addresses are to be shared between the plurality of processors.
5 . The processor of claim 1 , wherein the one or more circuits are to perform a memory manager to coordinate the one or more shared virtual memory addresses between the plurality of processors.
6 . The processor of claim 1 , wherein the one or more shared virtual memory-addresses are to be provided to the API as a memory handle.
7 . The processor of claim 1 , wherein the one or more shared virtual memory addresses are to be allocated by a second API that causes the one or more shared virtual memory-addresses to be allocated for use by the plurality of processors.
8 . The processor of claim 1 , wherein the one or more circuits comprise a switch to route the one or more shared virtual memory addresses to one or more different physical memory addresses located on different processors.
9 . The processor of claim 1 , wherein at least one processor of the plurality of processors is a graphics processing unit (GPU).
10 . The processor of claim 1 , wherein:
a first processor of the plurality of processors is of a first node of a compute cluster;
a second processor of the plurality of processors is of a second node of the compute cluster; and
the first processor is to access memory of the second processor using the one or more shared virtual memory addresses.
11 . The processor of claim 1 , wherein the one or more circuits are to further cause at least one processor of the plurality of processors to designate the one or more physical memory addresses to the one or more shared virtual memory addresses of a shared virtual memory.
12 . A computer-implemented method comprising: performing an application programming interface (API) to receive a location of one or more physical memory addresses and cause the one or more physical memory addresses to be assigned to one or more shared virtual memory addresses to be used by the plurality of processors.
13 . The computer-implemented method of claim 12 , wherein the one or more physical memory addresses comprise an address of multicast memory.
14 . The computer-implemented method of claim 12 , wherein:
a first processor of the plurality of processors is on a first node of a compute cluster; and
a second processor of the plurality of processors is on a second node of the compute cluster.
15 . The computer-implemented method of claim 12 , further comprising:
sharing the one or more shared virtual memory addresses between the plurality of processors using a memory handle.
16 . The computer-implemented method of claim 12 , further comprising:
performing a memory manager to coordinate the one or more shared virtual memory addresses between the plurality of processors.
17 . The computer-implemented method of claim 12 , wherein performing the API comprises:
selecting a processor of the plurality of processors;
allocating a physical memory location in memory of the processor; and
mapping the physical memory location to the one or more shared virtual memory addresses.
18 . The computer-implemented method of claim 12 , wherein at least one processor of the plurality of processors is a graphics processing unit (GPU).
19 . The computer-implemented method of claim 12 , further comprising:
routing the one or more shared virtual memory addresses to one or more different physical memory addresses located on a different device.
20 . The computer-implemented method of claim 12 , further comprising:
performing one or more compute operations using the one or more shared virtual memory addresses.
21 . The computer-implemented method of claim 12 , wherein a set processors of the plurality of processors are to share a first memory handle corresponding to the one or more shared virtual memory addresses.
22 . The computer-implemented method of claim 12 , wherein:
a set of processors of the plurality of processors are to share a first memory handle corresponding to a first virtual memory address of the one or more shared virtual memory addresses; and
a subset of the set of processors are to share a second memory handle corresponding to a second virtual memory address.
23 . A computer system comprising:
one or more processors and memory storing executable instructions that, as a result of being executed by the one or more processors, cause the one or more processors to perform an application programming interface (API) to receive a location of one or more physical memory addresses and cause the one or more physical memory addresses to be assigned to one or more shared virtual memory addresses to be used by a plurality of processors.
24 . The computer system of claim 23 , wherein the one or more shared virtual memory addresses correspond to an address of multicast memory.
25 . The computer system of claim 23 , wherein:
a first processor of the plurality of processors is to be on a first device; and
a second processor of the plurality of processors is to be on a second device.
26 . The computer system of claim 23 , wherein the one or more shared virtual memory addresses are to be shared between the plurality of processors.
27 . The computer system of claim 23 , wherein the one or more processors are to perform a load operation using the one or more shared virtual memory addresses.
28 . The computer system of claim 23 , wherein the one or more processors are to perform a store operation using the one or more shared virtual memory addresses.
29 . The computer system of claim 23 , wherein the one or more processors are to perform an atomic operation using the one or more shared virtual memory addresses.
30 . The computer system of claim 23 , wherein the one or more processors are to perform a load operation with reduction using the one or more shared virtual memory addresses.
31 . The computer system of claim 23 , wherein the one or more processors are to perform an atomic operation with reduction using the one or more shared virtual memory addresses.
32 . A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to perform an application programming interface (API) to receive a location of one or more physical memory addresses and cause the one or more physical memory addresses to be assigned to one or more shared virtual memory addresses to be used by a plurality of processors.
33 . The machine-readable medium of claim 32 ,
wherein the one or more shared virtual memory addresses comprise an address of multicast memory.
34 . The machine-readable medium of claim 32 ,
wherein the one or more shared virtual memory addresses comprise an address of unicast memory.
35 . The machine-readable medium of claim 32 , wherein:
a first processor of the plurality of processors is to be on a first node of a compute cluster; and
a second processor of the plurality of processors is to be on a second node of the compute cluster.
36 . The machine-readable medium of claim 32 , wherein the one or more shared virtual memory addresses are to be shared between the plurality of processors.
37 . The machine-readable medium of claim 32 , wherein the API is to receive a memory handle that at least indicates the one or more shared virtual memory addresses.
38 . The machine-readable medium of claim 35 , wherein the first processor is to access memory of the second processor using the one or more shared virtual memory addresses.
39 . The machine-readable medium of claim 32 , wherein the API is to receive a set of flags that indicate one or more properties of the one or more shared virtual memory addresses.
40 . The machine-readable medium of claim 32 , wherein the API is to return a success indicator to a calling process executing on a processor of the one or more processors.
41 . A processor comprising:
one or more circuits to perform an application programming interface (API) to cause one or more physical memory addresses to be assigned to one or more shared virtual memory addresses to be used by a plurality of processors, wherein a first processor of the plurality of processors is of a first node of a compute cluster, a second processor of the plurality of processors is of a second node of the compute cluster, and the first processor is to access memory of the second processor using the one or more shared virtual memory addresses.