Digitally controlled delay line with tunable ranges
A delay-line circuit that includes both fixed-delay line circuit and a variable delay-line circuit is disclosed. The fixed delay-line circuit may generate a first output clock signal by delaying an input clock signal by a particular delay period. The variable delay-line circuit may include multiple fixed-delay circuits and variable-delay circuits, and may select a particular subset of the fixed-delay circuits and the variable delay circuits based on a frequency of the input clock signal. The particular subset of the fixed-delay and variable-delay circuits may generate a second output clock signal by delaying the input clock signal by another delay period different than the particular delay period.
1 . An apparatus, comprising:
a fixed delay-line circuit configured, in response to a given transition on an input clock signal, to generate a first corresponding transition on a first output clock signal after a particular delay period has elapsed; and
a variable delay-line circuit that includes a plurality of fixed-delay circuits and a plurality of variable-delay circuits, wherein the variable delay-line circuit is configured to:
select, based on a frequency of the input clock signal, a particular subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits; and
generate, in response to the particular subset receiving the given transition, a second corresponding transition on a second output clock signal after a different delay period has elapsed.
2 . The apparatus of claim 1 , wherein to select the particular subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits, the variable delay-line circuit is further configured, in response to a determination that the input clock signal has a first frequency, to select a first subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits that includes a first fixed-delay circuit of the plurality of fixed-delay circuits coupled in series with a first variable-delay circuit of the plurality of variable-delay circuits.
3 . The apparatus of claim 2 , wherein the variable delay-line circuit is further configured, in response to a determination that the input clock signal has a second frequency less than the first frequency, to select a second subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits that includes the first subset coupled, in series, with a second fixed-delay circuit of the plurality of fixed-delay circuits.
4 . The apparatus of claim 3 , wherein the variable delay-line circuit is further configured, in response to a determination that the input clock signal has a third frequency less than the second frequency, to select a third subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits that includes the second subset coupled, in series, with a third fixed-delay circuit of the plurality of fixed-delay circuits and a second variable-delay circuit of the plurality of variable-delay circuits.
5 . The apparatus of claim 4 , wherein the variable delay-line circuit is further configured, in response to a determination that the input clock signal has a fourth frequency less than the third frequency, to select a fourth subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits that includes the third subset coupled, in series, with a fourth fixed-delay circuit of the plurality of fixed-delay circuits.
6 . The apparatus of claim 1 , wherein the plurality of variable-delay circuits includes a given variable-delay circuit configured, in response to a given transition on an input signal, to generate a corresponding transition on an output signal after a particular delay period has elapsed, wherein the particular delay period is based on at least one operating condition of a computer system that includes the variable delay-line circuit.
7 . A method, comprising:
generating, by a fixed delay-line circuit in response to a given transition on an input clock signal, a first corresponding transition on a first output clock signal after a particular delay period has elapsed;
selecting, by a variable delay-line circuit based on a frequency of the input clock signal, a particular subset of a plurality of fixed-delay circuits and a plurality of variable-delay circuits, wherein the plurality of fixed-delay circuits and the plurality of variable-delay circuits are included in the variable delay-line circuit; and
generating, by the variable delay-line circuit in response to the particular subset receiving the given transition, a second corresponding transition on a second output clock signal after a different delay period has elapsed.
8 . The method of claim 7 , wherein selecting the particular subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits includes, selecting, by the variable delay-line circuit in response to determining that the input clock signal has a first frequency, a first subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits that includes a first fixed-delay circuit of the plurality of fixed-delay circuits coupled in series with a first variable-delay circuit of the plurality of variable-delay circuits.
9 . The method of claim 8 , further comprising selecting, in response to determining that the input clock signal has a second frequency less than the first frequency, a second subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits that includes the first subset coupled, in series, with a second fixed-delay circuit of the plurality of fixed-delay circuits.
10 . The method of claim 9 , further comprising, selecting, by the variable delay-line circuit in response to determining that the input clock signal has third frequency less than the second frequency, a third subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits that includes the second subset coupled, in series, with a third fixed-delay circuit of the plurality of fixed-delay circuits and a second variable-delay circuit of the plurality of variable-delay circuits.
11 . The method of claim 10 , further comprising, selecting, by the variable delay-line circuit in response to determining that the input clock signal has a fourth frequency less than the third frequency, a fourth subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits that includes the third subset coupled, in series, with a fourth fixed-delay circuit of the plurality of fixed-delay circuits.
12 . The method of claim 7 , further comprising, generating, by a given variable-delay circuit in response to a given transition on an input signal, a corresponding transition on an output signal after a particular delay period has elapsed, wherein the particular delay period is based on at least one operating condition of a computer system that includes the variable delay-line circuit.
13 . An apparatus, comprising:
a first device coupled to a communication bus; and
a second device coupled to the communication bus wherein the second device includes
a fixed delay-line circuit configured, in response to a given transition on an input clock signal, to generate a first corresponding transition on a first output clock signal after a particular delay period has elapsed; and
a variable delay-line circuit that includes a plurality of fixed-delay circuits and a plurality of variable-delay circuits, wherein the variable delay-line circuit is configured to:
select, based on a frequency of the input clock signal, a particular subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits; and
generate, in response to the particular subset receiving the given transition, a second corresponding transition on a second output clock signal after a different delay period has elapsed.
14 . The apparatus of claim 13 , wherein to select the particular subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits, the variable delay-line circuit is further configured, in response to a determination that the input clock signal has a first frequency, to select a first subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits that includes a first fixed-delay circuit of the plurality of fixed-delay circuits coupled in series with a first variable-delay circuit of the plurality of variable-delay circuits.
15 . The apparatus of claim 14 , wherein the variable delay-line circuit is further configured, in response to a determination that the input clock signal has a second frequency less than the first frequency, to select a second subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits that includes the first subset coupled, in series, with a second fixed-delay circuit of the plurality of fixed-delay circuits.
16 . The apparatus of claim 15 , wherein the variable delay-line circuit is further configured, in response to a determination that the input clock signal has a third frequency less than the second frequency, to select a third subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits that includes the second subset coupled, in series, with a third fixed-delay circuit of the plurality of fixed-delay circuits and a second variable-delay circuit of the plurality of variable-delay circuits.
17 . The apparatus of claim 16 , wherein the variable delay-line circuit is further configured, in response to a determination that the input clock signal has a fourth frequency less than the third frequency, to select a fourth subset of the plurality of fixed-delay circuits and the plurality of variable-delay circuits that includes the third subset coupled, in series, with a fourth fixed-delay circuit of the plurality of fixed-delay circuits.
18 . The apparatus of claim 17 , wherein the plurality of variable-delay circuits includes a given variable-delay circuit configured, in response to a given transition on an input signal, to generate a corresponding transition on an output signal after a particular delay period has elapsed, wherein the particular delay period is based on at least one operating condition of a computer system that includes the variable delay-line circuit.