Nanosheet device with vertical blocker fin
A FET channel includes a stack of silicon nanosheets. The silicon nanosheets are oriented parallel to a planar portion of the FET in which the FET channel is formed. The FET channel also includes a vertical blocker fin. The vertical blocker fin is attached to at least one nanosheet in the stack of nanosheets.
1 . A nanosheet CMOS cell comprising:
a transistor region comprising a stack of nanosheet channels;
a vertical blocker fin attached to at least one channel of the stack of nanosheet channels; and
a bottom insolation layer immediately below the stack of nanosheet channels.
2 . The nanosheet CMOS cell of claim 1 , wherein at least a portion of the vertical blocker fin extends above a top surface of the stack of nanosheet channels.
3 . The nanosheet CMOS cell of claim 1 , further comprising:
a work function material between and physically separating the vertical blocker fin from the bottom insolation layer.
4 . The nanosheet CMOS cell of claim 1 , further comprising:
a gate dielectric between and physically separating the vertical blocker fin from the bottom insolation layer.
5 . The nanosheet CMOS cell of claim 1 , wherein each channel in the stack of nanosheet channels comprises a first end opposite a second end, wherein the vertical blocker fin contacts the first end of each channel in the stack of nanosheet channels, and wherein the second end of each channel in the stack of nanosheet channels is flush with a sidewall of the bottom insolation layer.
6 . The nanosheet CMOS cell of claim 1 , wherein the vertical blocker fin is entirely above the bottom insolation layer.
7 . The nanosheet CMOS cell of claim 1 , wherein each channel in the stack of nanosheet channels comprises a first end and a second end, wherein the vertical blocker fin contacts the first end of each channel in the stack of nanosheet channels, and wherein the second end of each channel in the stack of nanosheet channels is surrounded by a work function metal.
8 . A nanosheet CMOS cell comprising:
a stack of nanosheet channels;
a vertical blocker fin directly contacting first sidewalls of all channels of the stack of nanosheet channels; and
a bottom insolation layer immediately below the stack of nanosheet channels, wherein a sidewall of the bottom insolation layer is flush with second sidewalls of all the channels of the stack of nanosheet channels.
9 . The nanosheet CMOS cell of claim 8 , wherein at least a portion of the vertical blocker fin extends above a top surface of the stack of nanosheet channels.
10 . The nanosheet CMOS cell of claim 8 , further comprising:
a work function material between and physically separating the vertical blocker fin from the bottom insolation layer.
11 . The nanosheet CMOS cell of claim 8 , further comprising:
a gate dielectric between and physically separating the vertical blocker fin from the bottom insolation layer.
12 . The nanosheet CMOS cell of claim 8 , wherein the vertical blocker fin is entirely above the bottom insolation layer.
13 . The nanosheet CMOS cell of claim 8 , wherein the second sidewalls of all channels of the stack of nanosheet channels are surrounded by a work function metal.
14 . A nanosheet CMOS cell comprising:
a first transistor comprising a first stack of nanosheet channels;
a first vertical blocker fin in direct contact with ends of each channel of the first stack of nanosheet channels;
a first bottom insolation layer immediately below the first stack of nanosheet channels;
a second transistor adjacent to the first transistor, the second transistor comprising a second stack of nanosheet channels;
a second vertical blocker fin in direct contact with ends of each channel of the second stack of nanosheet channels; and
a second bottom insolation layer immediately below the second stack of nanosheet channels,
wherein both the first vertical blocker fin and the second vertical blocker fin are arranged between the first transistor and the second transistor.
15 . The nanosheet CMOS cell of claim 14 , wherein at least a portion of the first vertical blocker fin extends above a top surface of the first stack of nanosheet channels, and wherein at least a portion of the second vertical blocker fin extends above a top surface of the second stack of nanosheet channels.
16 . The nanosheet CMOS cell of claim 14 , further comprising:
a first work function material between and physically separating the first vertical blocker fin from the first bottom insolation layer; and
a second work function material between and physically separating the second vertical blocker fin from the second bottom insolation layer.
17 . The nanosheet CMOS cell of claim 14 , further comprising:
a gate dielectric between and physically separating the first vertical blocker fin from the first bottom insolation layer, wherein the gate dielectric is between and physically separating the second vertical blocker fin from the second bottom insolation layer.
18 . The nanosheet CMOS cell of claim 14 , wherein each channel in the first stack of nanosheet channels comprises a first end opposite a second end, wherein the first vertical blocker fin contacts the first end of each channel in the first stack of nanosheet channels, and wherein the second end of each channel in the first stack of nanosheet channels is flush with a sidewall of the first bottom insolation layer.
19 . The nanosheet CMOS cell of claim 14 , wherein the first vertical blocker fin is entirely above the first bottom insolation layer, and wherein the second vertical blocker fin is entirely above the second bottom insolation layer.
20 . The nanosheet CMOS cell of claim 14 , wherein each channel in the first stack of nanosheet channels comprises a first end and a second end, wherein the first vertical blocker fin contacts the first end of each channel in the first stack of nanosheet channels, and wherein the second end of each channel in the first stack of nanosheet channels is surrounded by a work function metal.