Stage and emission control driver having the same
A stage circuit including: an output circuit for supplying a voltage of a first or second power supply to an output terminal in response to voltages of first and second nodes; an input circuit for controlling voltages of the second node and a third node; a first signal processor for controlling the voltage of the first node; a second signal processor configured to control the voltage of the first node in response to an output voltage of a third signal processor and a signal supplied to a third input terminal; and the third signal processor for controlling the voltage of the second node. The third signal processor includes: a third capacitor coupled between the first power supply and the second node; and a third transistor coupled between the first power supply and the third input terminal, and including a gate electrode coupled to the second node.
1 . A stage circuit comprising:
a first transistor coupled between a first input terminal and a fourth node, wherein a gate electrode of the first transistor is coupled to a second input terminal;
a tenth transistor coupled between an output terminal and a second power supply line, where in a gate electrode of the tenth transistor is coupled to a second node;
a third capacitor coupled between the second node and a seventh node;
a third transistor coupled between the seventh node and a third input terminal wherein a gate electrode of the third transistor is coupled to the second node; and
a second transistor coupled between the seventh node and a first power supply line wherein a gate electrode of the second transistor is coupled to a third node,
wherein a first conductor comprising a first electrode of the third capacitor, the gate electrode of the third transistor, and the gate electrode of the tenth transistor is disposed in a first conductive layer, and
wherein the first conductor forms the second node.
2 . The stage circuit according to claim 1 , wherein source electrodes and drain electrodes of the first, third and second transistors are disposed in an active layer,
wherein the first conductor comprises a (1-1)-th conductor extending from the gate electrode of the third transistor to the gate electrode of the tenth transistor, and
wherein the (1-1)-th conductor does not overlap with a third conductive layer comprising the first power supply line and the second power supply line.
3 . The stage circuit according to claim 1 , wherein:
an active layer comprising source electrodes and drain electrodes of the first, third, and second transistors is disposed under the first conductive layer;
a first insulating layer is disposed on between the active layer and the first conductive layer;
a second insulating layer is disposed on the first conductive layer;
a second conductive layer comprising a second electrode of the third capacitor is disposed on the second insulating layer; and
a third insulating layer is disposed on the second conductive layer.
4 . The stage circuit according to claim 1 , wherein at least one of a so urce electrode or a drain electrode of the second transistor is directly coupled with at least one of a source electrode or a drain electrode of the third transistor.
5 . The stage circuit according to claim 1 , further comprising,
a fourth transistor coupled between the second input terminal and the third node wherein a gate electrode of the fourth transistor is coupled to the fourth node.
6 . The stage circuit according to claim 5 , wherein the fourth transistor comprises,
a plurality of sub-transistors coupled in series between the third node and the second input terminal and gate electrodes of the plurality of sub-transistors are coupled to the fourth node.
7 . The stage circuit according to claim 1 , further comprising,
a fifth transistor coupled between the second power supply line and the third node wherein a gate electrode of the fifth transistor is coupled to the second input terminal.
8 . The stage circuit according to claim 1 , further comprising,
a twelfth transistor coupled between the fourth node and the gate electrode of the tenth transistor, wherein a gate electrode of the twelfth transistor is coupled to the second power supply line.
9 . The stage circuit according to claim 8 , further comprising,
an eleventh transistor coupled between a fifth node and the gate electrode of the second transistor, wherein a gate electrode of the eleventh transistor is coupled to the second power sup ply line.
10 . The stage circuit according to claim 1 , further comprising,
a ninth transistor coupled between the first power supply line and the output terminal, where in a gate electrode of the ninth transistor is coupled to a first node;
a seventh transistor coupled between the first node and a sixth node, wherein a gate electrode of the seventh transistor is coupled to the third input terminal; and
a second capacitor coupled between the sixth node and a fifth node, wherein:
the gate electrode of the ninth transistor is disposed in the same layer as the first electrode of the third capacitor; and
a first electrode of the second capacitor is disposed in the same layer as the first electrode of the third capacitor.
11 . The stage circuit according to claim 10 , further comprising,
a sixth transistor coupled between the sixth node and the third input terminal, wherein a gate electrode of the sixth transistor is coupled to the fifth node.
12 . The stage circuit according to claim 10 , further comprising,
a first capacitor coupled between the first power supply line and the first node,
wherein a first electrode of the first capacitor is disposed in the same layer as the first electrode of the third capacitor.
13 . The stage circuit according to claim 10 , further comprising,
an eighth transistor coupled between the first power supply line and the first node, wherein a gate electrode of the eight transistor is coupled to the second node.
14 . The stage circuit according to claim 1 ,
wherein the first input terminal is coupled to an output terminal of a previous stage.
15 . The stage circuit according to claim 1 ,
wherein the second input terminal is supplied with a first clock signal, the third input terminal is supplied with a second clock signal, and the first clock signal and the second clock signal have identical waveforms with a phase difference of a half cycle or more.
16 . The stage circuit according to claim 1 ,
wherein the first transistor, the second transistor, the third transistor and the tenth transistor a re each a p-type transistor.
17 . The stage circuit according to claim 1 , further comprising,
a thirteenth transistor and a fourteenth transistor connected in series between the first power supply line and the fourth node,
wherein a gate electrode of the thirteenth transistor is coupled to the third node, and
wherein a gate electrode of the fourteenth transistor is coupled to the third input terminal.