Inductor based tail current source for current steering DAC
In one embodiment, the disclosure relates to a current steering DAC system. The system may include a current steering digital to analogy converter (DAC) that includes a clock buffer configured to generate a first clock signal having a first frequency and a second clock signal having a second frequency; a tail node; a first clock switch in electrical communication with the tail node; a second clock switch in electrical communication with the tail node; and a current source comprising an inductor having an inductance, the current source in electrical communication with the tail node.
1 . A system comprising:
a current steering digital to analog converter (DAC) comprising,
a clock buffer configured to generate a first clock signal having a first frequency and a second clock signal having a second frequency;
a tail node;
a first clock switch in electrical communication with the tail node;
a second clock switch in electrical communication with the tail node;
a current source comprising an inductor having an inductance L, the current source in electrical communication with the tail node; and
one or more data switches in electrical communication with the first clock switch and second clock switch and configured to receive digital communication data that is converted to analog signals, wherein the first clock switch and second clock switch are positioned between the one or more data switches and the inductor.
2 . The system of claim 1 , wherein the first frequency is f CLK and the second frequency is f CLK .
3 . The system of claim 1 wherein the inductor is configured to resonate at a frequency of 2 f CLK and thereby reduce a parasitic capacitance of the current source.
4 . The system of claim 3 , wherein inductance at the tail node is tuned until 2f CLK =1/2π√{square root over (LC parasite )}, wherein C parasitic is the parasitic capacitance of the current source.
5 . The system of claim 4 , wherein the current at the tail node is tuned by controlling a common mode voltage of the first clock switch and the second clock switch.
6 . The system of claim 4 , wherein the current at the tail node is tuned by controlling a common mode voltage by using a replica segment and measure an output current from the replica segment.
7 . The system of claim 1 , wherein the inductor is directly coupled to the tail node.
8 . The system of claim 7 , wherein first clock switch is a MOS transistor and the second clock switch is a MOS transistor.
9 . A method comprising:
providing a current steering digital to analog converter (DAC) comprising a clock buffer;
providing a current source comprising an inductor having an inductance L, the current source in electrical communication with a tail node;
generating, using the clock buffer, a first clock signal having a first frequency;
generating, using the clock buffer, a second clock signal having a second frequency, wherein the first frequency is f CLK and the second frequency is f CLK ;
resonating the inductor at a frequency of about 2f CLK ; and
receiving, at one or more data switches in electrical communication with a first clock switch and a second clock switch, digital communication data that is converted to analog signals, wherein the first clock switch and second clock switch are positioned between the one or more data switches and the inductor.
10 . The method of claim 9 further comprising: tuning the inductance L until
2
f
CLK
=
1
2
π
L
C
parasitic
,
wherein C parasitic is a parasitic capacitance of the current source.
11 . The method of claim 9 further comprising: controlling a common mode voltage of the first clock switch and the second clock switch to tune the current at the tail node.
12 . The method of claim 9 further comprising: controlling a common mode voltage by using a replica segment and measure an output current from the replica segment to tune the current at the tail node.
13 . The method of claim 9 , further comprising: reducing a parasitic capacitance of the current source in response to resonating the inductor at a frequency of 2f CLK .
14 . The method of claim 9 further comprising: tuning the current at the tail node by controlling a common mode voltage by using a replica segment and measure an output current from the replica segment.
15 . The method of claim 9 , wherein the inductor is directly coupled to the tail node.
16 . The method of claim 9 further comprising: tuning the current at a tail node by controlling a common mode voltage of a first clock switch and a second clock switch.
17 . The method of claim 16 , wherein the first clock switch is in electrical communication with the tail node.
18 . The method of claim 17 , wherein the second clock switch is in electrical communication with the tail node.
19 . The method of claim 18 , wherein the first clock switch is a MOS transistor and the second clock switch is a MOS transistor.
20 . A system comprising:
a current steering digital to analog converter (DAC) comprising,
a clock buffer configured to generate a first clock signal having a first frequency and a second clock signal having a second frequency;
a tail node;
a first clock switch in electrical communication with the tail node;
a second clock switch in electrical communication with the tail node; and
a current source comprising an inductor having an inductance L, the current source in electrical communication with the tail node, wherein inductance at the tail node is tuned until 2f CLK =1/2π√{square root over (LC parasite )}, wherein C parasitic is the parasitic capacitance of the current source.