Ballistic superconducting circuit for asynchronous reversible logic element
A ballistic, asynchronous logic circuit includes a controlled barrier which has a reversible memory cell and a polarity filter. The polarity filter is inductively coupled to the reversible memory cell. The circuit includes first and second polarity separators connected to the controlled barrier. The circuit includes a circulator connected to the controlled barrier.
1 . A ballistic, asynchronous logic circuit comprising: a pair of control inputs; a pair control outputs; a pair of data inputs; a pair of data outputs; a pair of complementary data outputs; a first polarity separator having a pair of first terminals connected to the control inputs and having a pair of second terminals and a pair of third terminals; a circulator having a pair of first terminals connected to the pair of data inputs, a pair of second terminals connected to the pair of complementary data outputs and having a pair of third terminals; a second polarity separator having a pair of first terminals, a pair of second terminals connected to the second terminals of the first polarity selector and a pair of third terminals connected to the control outputs; and a superconducting controlled barrier having a pair of first terminals connected to the third terminals of the first polarity selector, a pair of second terminals connected to the third terminals of the circulator, a pair of third terminals connected to the first terminals of the second polarity selector and a pair of fourth terminals connected to the pair of complementary data outputs.
2 . The circuit of claim 1 , wherein the superconducting controlled barrier comprises: a reversible memory cell having a pair of first terminals connected to the third terminals of the first polarity separator and a pair of second terminals connected to the first terminals of the second polarity separator; and a polarity filter inductively coupled to the reversible memory cell and having a pair of first terminals connected to the third terminals of the circulator and a pair of second terminals connected to the pair of complementary data outputs.
3 . The circuit of claim 2 , wherein a circulating current in the reversible memory cell induces an oppositely circulating current in the polarity filter.
4 . The circuit of claim 2 , wherein the reversible memory cell comprises:
a first inductor having first and second terminals;
a second inductor having first and second terminals;
a first Josephson Junction having a first terminal coupled to the first terminal of the first inductor and a second terminal connected to the first terminal of the second inductor;
a second Josephson Junction having a first terminal coupled to the second terminal of the first inductor and a second terminal connected to the second terminal of the second terminal.
5 . The circuit of claim 2 , wherein the polarity filter comprises:
a first inductor having first and second terminals;
a second inductor having first and second terminals;
a third inductor having first and second terminals;
a fourth inductor having first and second terminals;
a Josephson Junction comprising:
a first terminal coupled to the second terminal of the first inductor and connected to the first terminal of the second inductor;
a second terminal connected to the second terminal of the third inductor and connected to the first terminal of the fourth inductor.
6 . The circuit of claim 1 , wherein:
the pair of control inputs are configured to receive control input fluxons; and
the pair control outputs are configured to provide control output fluxons.
7 . The circuit of claim 1 , wherein:
the pair of data inputs are configured to receive input data fluxons;
the pair of data outputs are configured to provide output data fluxons; and
the pair of complementary data outputs are configured to provide complementary output data fluxons.
8 . A ballistic, asynchronous logic circuit comprising:
a first polarity separator having a pair of first terminals coupled to receive to control input fluxons and having a pair of second terminals and a pair of third terminals;
a circulator having a pair of first terminals coupled to receive to data input fluxons, a pair of second terminals configured to provide complementary output data fluxons and having a pair of third terminals;
a second polarity separator having a pair of first terminals, a pair of second terminals connected to the second terminals of the first polarity separator and a pair of third terminals configured to provide control output fluxons; and
a superconducting controlled barrier having a pair of first terminals connected to the third terminals of the first polarity selector, a pair of second terminals connected to the third terminals of the circulator, a pair of third terminals connected to the first terminals of the second polarity selector and a pair of fourth terminals configured to provide output data fluxons.
9 . The circuit of claim 8 , wherein the superconducting controlled barrier comprises:
a reversible memory cell having a pair of first terminals connected to the third terminals of the first polarity separator and a pair of second terminals connected to the first terminals of the second polarity separator; and
a polarity filter inductively coupled to the reversible memory cell and having a pair of first terminals connected to the third terminals of the circulator and a pair of second terminals configured to provide the complementary output data fluxons.
10 . The circuit of claim 9 , wherein a circulating current in the reversible memory cell induces an oppositely circulating current in the polarity filter.
11 . The circuit of claim 9 , wherein the reversible memory cell comprises:
a first inductor having first and second terminals;
a second inductor having first and second terminals;
a first Josephson Junction having a first terminal coupled to the first terminal of the first inductor and a second terminal connected to the first terminal of the second inductor;
a second Josephson Junction having a first terminal coupled to the second terminal of the first inductor and a second terminal connected to the second terminal of the second terminal.
12 . The circuit of claim 9 , wherein the polarity filter comprises:
a first inductor having first and second terminals;
a second inductor having first and second terminals;
a third inductor having first and second terminals;
a fourth inductor having first and second terminals;
a Josephson Junction having a first terminal coupled to the second terminal of the first inductor and connected to the first terminal of the second inductor and having a second terminal connected to the second terminal of the third inductor and connected to the first terminal of the fourth inductor.
13 . A superconducting controlled barrier comprising:
a reversible memory cell comprising:
a pair of first terminals configured to receive control fluxons and a pair of second terminals configured to receive ejected fluxons; and
a polarity filter comprising:
a pair of first terminals configured to receive input data fluxons;
a pair of second terminals configured to provide output data fluxons,
wherein the polarity filter is inductively coupled to the reversible memory cell.
14 . The controlled barrier of claim 13 , wherein a circulating current in the reversible memory cell induces an oppositely circulating current in the polarity filter.
15 . The controlled barrier of claim 13 , wherein the reversible memory cell comprises:
a first inductor having first and second terminals;
a second inductor having first and second terminals;
a first Josephson Junction having a first terminal coupled to the first terminal of the first inductor and a second terminal connected to the first terminal of the second inductor;
a second Josephson Junction having a first terminal coupled to the second terminal of the first inductor and a second terminal connected to the second terminal of the second terminal.
16 . The controlled barrier of claim 13 , wherein the polarity filter comprises:
a first inductor having first and second terminals;
a second inductor having first and second terminals;
a third inductor having first and second terminals;
a fourth inductor having first and second terminals;
a Josephson Junction comprising:
a first terminal coupled to the second terminal of the first inductor and connected to the first terminal of the second inductor;
a second terminal connected to the second terminal of the third inductor and connected to the first terminal of the fourth inductor.
17 . The controlled barrier of claim 13 , wherein the controlled barrier is set to a blocking state by applying a control fluxon of negative polarity to the reversible memory cell.
18 . The controlled barrier of claim 13 , wherein the controlled barrier is set to a passing state by applying a control a fluxon of positive polarity to the reversible cell.
19 . The controlled barrier of claim 17 , wherein the polarity filter reflects data fluxons in the blocking state.
20 . The controlled barrier of claim 18 , wherein the polarity filter allows data fluxons to pass through in the passing state.