Integration scheme for fabricating high precision, low capacitor with unlanded via
Semiconductor devices including a capacitor and methods of fabricating the semiconductor devices are disclosed. A method of fabricating a semiconductor device including a capacitor includes forming an underlayer structure including a substrate onto which metal is patterned within a first dielectric material, wherein the patterned metal forms a first metal surface of the capacitor; forming a middle layer of a second dielectric material above the underlayer structure; forming an upper layer of a third dielectric material above the middle layer; etching a supervia though the upper layer and into the middle layer, wherein the supervia hangs in the second dielectric material of the middle layer above the patterned metal forming the first metal surface of the capacitor; and performing barrier deposition and metal electroplating in the supervia, wherein the supervia forms a second metal surface of the capacitor above the first metal surface.
1 . A method of fabricating a semiconductor device including a capacitor, the method comprising:
forming an underlayer structure including a substrate onto which patterned metal is formed within a first dielectric material of the substrate, wherein the patterned metal forms a first metal surface of the capacitor;
forming a middle layer of a second dielectric material above the underlayer structure;
forming an upper layer of a third dielectric material above the middle layer;
etching a supervia through the upper layer and into the middle layer, wherein the supervia is disposed in the second dielectric material of the middle layer above the patterned metal forming the first metal surface of the capacitor; and
performing barrier deposition and metal electroplating in the supervia, wherein a metal on the supervia forms a second metal surface of the capacitor above the first metal surface.
2 . The method of claim 1 , further comprising performing patterning and metallization on at least one of the middle layer or the upper layer.
3 . The method of claim 1 , further comprising forming an etch stop layer on top of at least one of the underlayer structure or the middle layer.
4 . The method of claim 1 , further comprising performing post-chemical mechanical polishing (CMP) capping on the upper layer before etching the supervia.
5 . The method of claim 4 , further comprising performing supervia patterning on the post-CMP cap,
wherein the supervia is etched according to the supervia patterning.
6 . The method of claim 1 , further comprising forming a capping layer onto the upper layer after performing barrier deposition and metal electroplating in the supervia.
7 . The method of claim 1 , wherein the first dielectric material, the second dielectric material, and the third dielectric material include a same dielectric material.
8 . A method of fabricating a semiconductor device including a capacitor, the method comprising:
forming an underlayer structure including a substrate onto which patterned metal is formed within a first dielectric material of the substrate, wherein the patterned metal forms a first metal surface of the capacitor;
forming a middle layer of a second dielectric material above the underlayer structure;
forming an upper layer of a third dielectric material above the middle layer;
forming an unlanded via through the upper layer and into the middle layer, wherein the unlanded via is disposed in the second dielectric material of the middle layer above the patterned metal forming the first metal surface of the capacitor; and
performing barrier deposition and metal electroplating on the upper layer, wherein a metal on the unlanded via forms a second metal surface of the capacitor above the first metal surface.
9 . The method of claim 8 , further comprising performing patterning and metallization on the middle layer.
10 . The method of claim 8 , further comprising forming an etch stop layer on top of at least one of the underlayer structure or the middle layer.
11 . The method of claim 8 , further comprising forming a patterning film layer on the upper layer before forming an unlanded via.
12 . The method of claim 11 , wherein the patterning film layer includes at least one of a first dielectric hard mask layer, a metal hard mask (MHM) layer, or a second dielectric hard mask layer.
13 . The method of claim 11 , further comprising creating open areas of the patterning film layer by performing trench patterning.
14 . The method of claim 13 , wherein forming the unlanded via comprises:
performing via patterning and via etching on the opened areas; and
performing final etching and cleaning on the patterned and etched via.
15 . The method of claim 8 , further comprising forming a capping layer onto the upper layer after performing barrier deposition and metal electroplating on the upper layer.
16 . The method of claim 8 , wherein the first dielectric material, the second dielectric material, and the third dielectric material include a same dielectric material.