Feedback-reinforced accelerated aging for improved PUF stability
View Patent ↗A method of operating a chip as an entropy source for generating a physical unclonable function (PUF) key includes: arranging in the chip a pre-amplifier array of bitcells in respective rows defined by respective pairs of true and complement wordlines and in columns defined by respective pairs of true and complement bitlines; reading, by a sense amplifier, a preferred state from a bitcell along a selected pair of the pairs of true and complement wordlines, where the pre-amplifier array of bitcells comprises the bitcell; performing feedback-reinforced accelerated aging via control circuitry in the chip including, based on the read preferred state, applying a stress condition that causes an accelerated aging effect including biasing the bitcell to the preferred state to reinforce the preferred state in the bitcell; subsequent to performing the feedback-reinforced accelerated aging, reading a value from the bitcell; and generating a PUF key using the value.
1 . A method of operating a chip as an entropy source for generating a physical unclonable function (PUF) key, the method comprising:
arranging in the chip a pre-amplifier array of bitcells in respective rows defined by respective pairs of true and complement wordlines and in columns defined by respective pairs of true and complement bitlines;
reading, by a first sense amplifier integrated in the chip and connected to a first pair of the pairs of true and complement bitlines, a first preferred state from a first bitcell along a first selected pair of the pairs of true and complement wordlines, wherein the pre-amplifier array of bitcells comprises the first bitcell;
performing feedback-reinforced accelerated aging via control circuitry in the chip including, based on the read first preferred state, applying a first stress condition that causes an accelerated aging effect in the first bitcell, wherein applying the first stress condition comprises biasing the first bitcell to the first preferred state to reinforce the first preferred state in the first bitcell;
subsequent to performing the feedback-reinforced accelerated aging, reading a first value from the first bitcell; and
generating a first PUF key using the first value.
2 . The method according to claim 1 , wherein applying the first stress condition comprises:
applying a first voltage to a first portion of the first bitcell, which is biased toward the first preferred state; and
applying a second voltage to a second portion of the first bitcell, which is biased away from the first preferred state, the second voltage being less than the first voltage.
3 . The method according to claim 1 , wherein applying the first stress condition comprises applying the first stress condition for longer than a threshold duration.
4 . The method according to claim 1 , wherein applying the first stress condition comprises causing the first bitcell to exhibit one or more of (1) biased temperature instability or (2) hot carrier injection.
5 . The method according to claim 1 , further comprising:
reading, by a second sense amplifier connected to a second pair of the pairs of true and complement bitlines, a second preferred state from a second bitcell along the first selected pair of the pairs of true and complement wordlines, wherein the pre-amplifier array of bitcells comprises the second bitcell;
performing feedback-reinforced accelerated aging including, based on the second preferred state, applying a second stress condition that causes an accelerated aging effect in the second bitcell, wherein applying the second stress condition comprises biasing the second bitcell to the second preferred state to reinforce the second preferred state in the second bitcell; and
subsequent to performing the feedback-reinforced accelerated aging on the second bitcell, reading a second value from the first bitcell,
wherein generating the first PUF key further comprises using the second value.
6 . The method according to claim 5 , wherein the first stress condition and the second stress condition are applied simultaneously.
7 . The method according to claim 5 , wherein:
applying the first stress condition to the first bitcell comprises activating a first source voltage local to the first bitcell; and
applying the second stress condition to the second bitcell comprises applying a second source voltage local to the second bitcell.
8 . The method according to claim 5 , wherein applying the first stress condition to the first bitcell and applying the second stress condition to the second bitcell comprise applying a source voltage to the first selected pair of the pairs of true and complement wordlines.
9 . The method according to claim 5 , further comprising, after reading the first value from the first bitcell, deactivating the first bitcell by applying a zero voltage to the true wordline of the selected pair of the pairs of true and complement wordlines and by applying a source voltage to the complement wordline of the selected pair of the pairs of true and complement wordlines to prevent the first value from being read outside of the chip.
10 . A chip operating as an entropy source for generating a physical unclonable function (PUF) key, the chip comprising:
a pre-amplifier array of bitcells arranged in respective rows defined by respective pairs of true and complement wordlines and in columns defined by respective pairs of true and complement bitlines;
a first sense amplifier connected to a first pair of the pairs of true and complement bitlines and configured to read a first preferred state from a first bitcell of the pre-amplifier array of bitcells along a first selected pair of the pairs of true and complement wordlines; and
control circuitry within the chip and configured to perform feedback-reinforced accelerated aging including, based on the read first preferred state, applying a first stress condition that causes an accelerated aging effect in the first bitcell, wherein applying the first stress condition comprises biasing the first bitcell to the first preferred state to reinforce the first preferred state in the first bitcell,
wherein
the first sense amplifier is further configured, subsequent to performing the feedback-reinforced accelerated aging, to read a first value from the first bitcell, and
the chip further comprises key generation circuitry configured to generate a first PUF key using the first value.
11 . The chip according to claim 10 , wherein the control circuitry is configured, when applying the first stress condition, to:
apply a first voltage to a first portion of the first bitcell, which is biased toward the first preferred state, and
apply a second voltage to a second portion of the first bitcell, which is biased away from the first preferred state, the second voltage being less than the first voltage.
12 . The chip according to claim 10 , wherein the control circuitry is configured, when applying the first stress condition, to apply the first stress condition for longer than a threshold duration.
13 . The chip according to claim 10 , wherein the control circuitry is configured, when applying the first stress condition, to cause the first bitcell to exhibit one or more of (1) biased temperature instability or (2) hot carrier injection.
14 . The chip according to claim 10 , further comprising a second sense amplifier connected to a second pair of the pairs of true and complement bitlines and configured to read a second preferred state from a second bitcell along the first selected pair of the pairs of true and complement wordlines wherein:
the pre-amplifier array of bitcells comprises the second bitcell;
the control circuitry is further configured to perform feedback-reinforced accelerated aging including, based on the second preferred state, applying a second stress condition that causes an accelerated aging effect in the second bitcell, wherein applying the second stress condition comprises biasing the second bitcell to the second preferred state to reinforce the second preferred state the second bitcell; and
subsequent to performing the feedback-reinforced accelerated aging on the second bitcell, the second sense amplifier is further configured to read a second value from the second bitcell; and
the key generation circuitry is configured to generate the first PUF key using the second value.
15 . The chip according to claim 14 , wherein the control circuitry is further configured to apply the first stress condition and the second stress condition simultaneously.
16 . The chip according to claim 14 , wherein the control circuitry is further configured to:
when applying the first stress condition to the first bitcell, activate a first source voltage local to the first bitcell; and
when applying the second stress condition to the second bitcell, apply a second source voltage local to the second bitcell.
17 . The chip according to claim 14 , wherein the control circuitry is further configured to, when applying the first stress condition to the first bitcell and applying the second stress condition to the second bitcell, apply a source voltage to the first selected pair of true and complement wordlines.
18 . The chip according to claim 10 , wherein the control circuitry is further configured to, after reading the first value from the first bitcell, deactivate the first bitcell by applying a zero voltage to the true wordline of the selected pair of true and complement wordlines and by applying a source voltage to the complement wordline of the selected pair of true and complement wordlines to prevent the first value from being read outside of the chip.
19 . The chip of claim 10 , wherein the first sense amplifier is configured, in reading the first preferred state, to:
sense a state of the first bitcell; and
output the first preferred state based on the sensed state of the first bitcell.
20 . The chip of claim 10 , further comprising imbalance circuitry connected to the pairs of true and complement bitlines,
wherein the control circuitry is connected to the first sense amplifier and provides feedback to the imbalance circuitry.
21 . The chip of claim 10 , further comprising imbalance circuitry connected to the pairs of true and complement bitlines,
wherein the control circuitry comprises i) a first plurality of gates connected to outputs of the first sense amplifier, and ii) a second plurality of gates providing feedback to the imbalance circuitry.
22 . The chip of claim 10 , further comprising imbalance circuitry connected to the pairs of true and complement bitlines, wherein:
the preferred state comprises a pair of bits;
the control circuitry comprises
a first pair of gates configured to receive respectively the pair of bits, and
a second pair of gates configured to receive outputs of the first pair of gates and generate control signals; and
the imbalance circuitry is configured, based on the control signals, to cause a current imbalance in a direction of the first preferred state of the first bitcell.
23 . The chip of claim 22 , wherein:
the control signals comprise a first control signal and a second control signal; and
the imbalance circuitry comprises
a first series of transistors connected to the complement bitline of the first bitcell and configured to receive the first control signal and, based on the first control signal, control current flow from the complement bitline to ground, and
a second series of transistors connected to the true bitline of the first bitcell and configured to receive the second control signal and, based on the second control signal, control current flow from the true bitline to the ground.