IP Library Granted Patent US 12,628,640
Granted Patent B2
US 12,628,640 · App. 17/357,773 · Granted May 12, 2026

Metal line profile shaping for advanced integrated circuit structure fabrication

Inventors: Leonard P. Guler (Hillsboro, OR); Tsuan-Chung Chang (Portland, OR); Michael James Makowski (Beaverton, OR); Benjamin Kriegel (Portland, OR); Robert Joachim (Beaverton, OR); Desalegne B. Teweldebrhan (Sherwood, OR); Charles H. Wallace (Portland, OR); Tahir Ghani (Portland, OR); Mohammad Hasan (Aloha, OR)
Assignee: Intel Corporation
H10W20/435H10W20/056H10W20/082H10W20/42
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Quick Facts
Patent No.
US 12,628,640
App. No.
17/357,773
Granted
May 12, 2026
Kind
B2
Abstract

Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a dielectric material structure having a trench therein. A conductive interconnect line in the trench, the conductive interconnect line having a length and a width, the width having a cross-sectional profile, wherein the cross-sectional profile of the width of the conductive interconnect line has a bottom lateral width, a mid-height lateral width, and a top lateral width, and wherein the mid-height lateral width is greater than the bottom lateral width, and the mid-height lateral width is greater than the top lateral width.

Claims (7)

1 . An integrated circuit structure, comprising:

a dielectric material structure having a trench therein;

a conductive interconnect line in the trench, the conductive interconnect line having a length and a cross-sectional profile orthogonal to the length, wherein the cross-sectional profile is a circular cross-sectional profile, wherein the circular cross-sectional profile has a bottom lateral width, a mid-height lateral width, and a top lateral width, and wherein the mid-height lateral width is greater than the bottom lateral width, and the mid-height lateral width is greater than the top lateral width; and

a conductive via coupled to conductive interconnect line, the conductive via having a center laterally offset from a center of the conductive line along a vertical axis, and the conductive via on a top and along a first side of the conductive interconnect line but not along a second side of the conductive line, the second side laterally opposite the first side.

2 . The integrated circuit structure of claim 1 , wherein the mid-height lateral width is at least 50% greater than the bottom lateral width and at least 50% greater than the top lateral width.

3 . The integrated circuit structure of claim 1 , wherein the circular cross-sectional profile has one or more scalloped surfaces.

4 . The integrated circuit structure of claim 1 , wherein the dielectric material structure comprises a stack of dielectric layers of differing composition.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2021
From: GULER, LEONARD P.; CHANG, TSUAN-CHUNG; MAKOWSKI, MICHAEL JAMES; KRIEGEL, BENJAMIN; JOACHIM, ROBERT; TEWELDEBRHAN, DESALEGNE B.; WALLACE, CHARLES H.; GHANI, TAHIR; HASAN, MOHAMMAD
To: INTEL CORPORATION
Reel/Frame 058271/0378 →
Continuity (1)
Related Publication 20220415791A1 · Dec 29, 2022
References Cited (6)
US 10355203B2 · Ito · 2019 [cited by examiner]
US 20040198057A1 · Huang · 2004 [cited by applicant]
US 20210091190A1 · Huang · 2021 [cited by applicant]
EP 1653509A2 · 2006 [cited by applicant]
Search Report from European Patent Application No. 22175145.6, mailed Nov. 21, 2022, 7 pgs. [cited by applicant]
Notice of Allowance from European Patent Application No. 22175145.6, mailed Sep. 19, 2025, 64 pgs. [cited by applicant]