Method and system to configure a neural processing unit
A method includes receiving one or more configuration parameters associated with a neural processing unit (NPU), wherein the one or more configuration parameters defines a number of processing tiles within the NPU, and wherein a processing tile includes a processing element of a first type configured to perform a dense operation, a processing element of a second type configured to perform a sparse operation, and an on-chip memory (OCM) associated therewith; and automatically generating the NPU based on the one or more configuration parameters and further based on a hardware descriptive language (HDL).
1 . A method, comprising:
receiving one or more configuration parameters associated with a neural processing unit (NPU), wherein the one or more configuration parameters defines a number of processing tiles within the NPU, and wherein a processing tile includes a processing element of a first type configured to perform a dense operation, a processing element of a second type configured to perform a sparse operation, and an on-chip memory (OCM) associated therewith; and
automatically generating the NPU based on the one or more configuration parameters and further based on a hardware descriptive language (HDL), wherein a number of double data rate (DDR) memory to the OCM via direct memory access (DMA) (DoD) is less than a number of the processing tiles arranged in a plurality of rows by a plurality of columns.
2 . The method of claim 1 , wherein the one or more configuration parameters defines a layout associated with the processing tiles.
3 . The method of claim 2 , wherein the layout includes a number of rows and a number of columns.
4 . The method of claim 1 , wherein the one or more configuration parameters defines a number of double data rate (DDR) memory to OCM via direct memory access (DMA) (DoD).
5 . The method of claim 4 , wherein the one or more configuration parameters defines a location or orientation associated with the DoD.
6 . The method of claim 1 , wherein the one or more configuration parameters define a size associated with OCM of the processing tile.
7 . The method of claim 1 , wherein the one or more configuration parameters is received via file in an extensible markup language (XML) format or yet another markup language (YAML) format.
8 . The method of claim 1 , wherein the HDL is a register transfer language (RTL).
9 . The method of claim 8 , wherein the RTL is templated using a templating language.
10 . The method of claim 9 , wherein the templating language is a Mako or Jinja.
11 . The method of claim 1 , wherein the generated NPU is in register transfer language (RTL) format.
12 . The method of claim 1 , wherein one of Python, Pearl, C, or tool command language (TCL) is used to automatically generate the NPU.
13 . The method of claim 1 , wherein the number of processing tiles is at least four.
14 . The method of claim 13 , wherein a maximum number of double data rate (DDR) memory to OCM via direct memory access (DMA) (DoD) is less than or equal to two for every four processing tiles arranged in a two by two rows and columns.
15 . A method, comprising:
receiving a file comprising one or more configuration parameters associated with a neural processing unit (NPU), wherein the one or more configuration parameters defines a layout associated with a plurality of processing tiles within the NPU, and wherein each processing tile within the plurality of processing tiles includes a processing element of a first type configured to perform a dense operation, a processing element of a second type configured to perform a sparse operation, and an on-chip memory (OCM) associated therewith; and
automatically generating the NPU based on the one or more configuration parameters and further based on a register transfer language (RTL), wherein a number of double data rate (DDR) memory to the OCM via direct memory access (DMA) (DoD) is less than a number of the processing tiles arranged in a plurality of rows by a plurality of columns.
16 . The method of claim 15 , wherein the layout includes one or more of a number of rows and a number of columns associated with the plurality of processing tiles and a number of double data rate (DDR) memory to OCM via direct memory access (DMA) (DoD).
17 . The method of claim 16 , wherein the layout further includes a location or orientation associated with the DoD.
18 . The method of claim 15 , wherein the layout further includes a size associated with OCM of a processing tile within the plurality of processing tiles.
19 . The method of claim 15 , wherein the file is in an extensible markup language (XML) format or yet another markup language (YAML) format.
20 . The method of claim 15 , wherein the RTL is templated using a templating language that includes a Mako or a Jinja.
21 . The method of claim 15 , wherein the generated NPU is in RTL format.
22 . The method of claim 15 , wherein one of Python, Pearl, C, or tool command language (TCL) is used to automatically generate the NPU.
23 . A system comprising:
a means for receiving a file comprising one or more configuration parameters associated with a neural processing unit (NPU), wherein the one or more configuration parameters defines a layout associated with a plurality of processing tiles within the NPU, and wherein each processing tile within the plurality of processing tiles includes a processing element of a first type configured to perform a dense operation, a processing element of a second type configured to perform a sparse operation, and an on-chip memory (OCM) associated therewith; and
a means for automatically generating the NPU based on the one or more configuration parameters and further based on a register transfer language (RTL), wherein a number of double data rate (DDR) memory to the OCM via direct memory access (DMA) (DoD) is less than a number of the processing tiles arranged in a plurality of rows by a plurality of columns.