Multi-charge pump structure with related method
The present disclosure relates to structures including charge pump structures and related methods of operating such structures. A structure of the disclosure includes a first charge pump stage including first branches each connected between an input voltage and ground. The first branches each include first capacitors (C 1 , C 2 ) connected between first intermediate nodes (Q 1 , Q 1 _B) and additional first intermediate nodes (V 1 , V 1 _B), respectively. A second charge pump stage includes second branches each connected between second intermediate nodes and additional second intermediate nodes, respectively.
1 . A structure comprising:
a first charge pump stage including first branches each connected between an input voltage node and ground, wherein the first branches each include first capacitors (C 1 , C 2 ) connected between first intermediate nodes (Q 1 , Q 1 _B) and additional first intermediate nodes (V 1 , V 1 _B), respectively, and wherein the first charge pump stage further includes:
two first p-channel field effect transistors connected in series between the additional first intermediate nodes (V 1 , V 1 _B), and
two additional first p-channel field effect transistors connected in series between the first intermediate nodes (Q 1 , Q 1 _B),
an additional first capacitor (C 3 ) connected between the input voltage node and a first output voltage node at a junction between the additional first p-channel field effect transistors, wherein the first output voltage node outputs a first output voltage at a magnitude of approximately two times the input voltage; and
a second charge pump stage including second branches, wherein the second branches each include second capacitors each connected between second intermediate nodes and additional second intermediate nodes, respectively, and wherein the second charge pump stage has a second output voltage node that outputs a second output voltage at a magnitude of approximately three times the input voltage.
2 . The structure of claim 1 , wherein:
the first branches include first n-channel field effect transistors, the first capacitors, and additional first n-channel field effect transistors connected in series between the input voltage node and ground, respectively,
the first intermediate nodes are between the first n-channel field effect transistors and the first capacitors, and
the additional first intermediate nodes are between the first capacitors and the additional first n-channel field effect transistors.
3 . The structure of claim 2 , wherein the first n-channel field effect transistors are cross-coupled to each other and wherein the additional first n-channel field effect transistors are controlled by a clock signal and an inverted clock signal, respectively.
4 . The structure of claim 3 , wherein the input voltage node is connected to receive an input voltage (Vin), and wherein the clock signal switches between the input voltage and ground.
5 . The structure of claim 1 , wherein
the first p-channel field effect transistors are controlled by the clock signal and the inverted clock signal, respectively; and
the two additional first p-channel field effect transistors are cross coupled to each other.
6 . The structure of claim 1 , wherein the additional first capacitor is smaller than the first capacitors.
7 . The structure of claim 1 , wherein a supply voltage (VDD) is coupled to a load capacitor through the first charge pump stage and the second charge pump stage, and one of the first capacitors in the first charge pump stage and a second capacitor within the second charge pump stage are connected in series between the supply voltage and the load capacitor.
8 . The structure of claim 1 , wherein at least one first capacitor of the first charge pump stage and at least one second capacitor of the second charge pump stage each couple a supply voltage to ground in parallel.
9 . A structure comprising:
a first charge pump stage including first branches each connected between an input voltage node and ground, wherein the first branches each include first capacitors (C 1 , C 2 ) connected between first intermediate nodes (Q 1 , Q 1 _B) and additional first intermediate nodes (V 1 , V 1 _B), respectively, and wherein the first charge pump stage further includes:
two first p-channel field effect transistors connected in series between the additional first intermediate nodes (V 1 , V 1 _B), wherein the first p-channel field effect transistors are controlled by a clock signal and an inverted clock signal, respectively, and
two additional first p-channel field effect transistors connected in series between the first intermediate nodes (Q 1 , Q 1 _B) and cross coupled to each other;
an additional first capacitor (C 3 ) connected between an input voltage node and a first output voltage node at a junction between the additional first p-channel field effect transistors, wherein the first output voltage node outputs a first output voltage at a magnitude of approximately two times the input voltage; and
a second charge pump stage including second branches, wherein the second branches each include second capacitors (C 4 , C 5 ) connected between second intermediate nodes (Q 2 , Q 2 _B) and additional second intermediate nodes (V 2 , V 2 _B), respectively, and wherein the second charge pump stage has a second output voltage node that outputs a second output voltage at a magnitude of approximately three times the input voltage.
10 . The structure of claim 9 , wherein:
the first branches include first n-channel field effect transistors, the first capacitors, and additional first n-channel field effect transistors connected in series between the input voltage node and ground,
the first intermediate nodes are between the first n-channel field effect transistors and the first capacitors, and
the additional first intermediate nodes are between the first capacitors and the additional first n-channel field effect transistors.
11 . The structure of claim 10 , wherein the first n-channel field effect transistors are cross-coupled to each other and wherein the additional first n-channel field effect transistors are controlled by the clock signal and the inverted clock signal, respectively.
12 . The structure of claim 11 , wherein the input voltage node is connected to receive an input voltage (Vin), and wherein the clock signal switches between the input voltage and ground.
13 . The structure of claim 9 , wherein a supply voltage (VDD) is coupled to a load capacitor through the first charge pump stage and the second charge pump stage, and one of the first capacitors in the first charge pump stage and a second capacitor within the second charge pump stage are connected in series between the supply voltage and the load capacitor.
14 . The structure of claim 13 , wherein at least one first capacitor of the first charge pump stage and at least one second capacitor of the second charge pump stage each couple the supply voltage to ground in parallel.
15 . A method comprising:
applying an input voltage to a first charge pump stage including first branches each connected between an input terminal and ground, wherein the first branches each include first capacitors (C 1 , C 2 ) connected between first intermediate nodes (Q 1 , Q 1 _B) and additional first intermediate nodes (V 1 , V 1 _B), respectively, and the first charge pump further includes two first p-channel field effect transistors connected in series between the additional first intermediate nodes (V 1 , V 1 _B) and two additional first p-channel field effect transistors connected in series between the first intermediate nodes (Q 1 , Q 1 _B);
connecting an additional first capacitor (C 3 ) between an input voltage node and a first output voltage node at a junction between the additional first p-channel field effect transistors, wherein applying the input voltage causes the first charge pump stage to output a first output voltage at a magnitude of approximately two times the input voltage; and
outputting a voltage from the first charge pump stage to a second charge pump stage including second branches each connected between second intermediate nodes (Q 2 , Q 2 _B) and additional second intermediate nodes (V 2 , V 2 _B), respectively, wherein the second branches include second capacitors (C 4 , C 5 ) connected between second intermediate nodes (Q 2 , Q 2 _B) and additional second intermediate nodes (V 2 , V 2 _B), and wherein the second charge pump stage outputs a second output voltage at a magnitude of approximately three times the input voltage.
16 . The method of claim 15 , further comprising:
coupling a supply voltage coupled to a load capacitor through the first charge pump stage and the second charge pump stage,
wherein one of the first capacitors in the first charge pump stage and a second capacitor within the second charge pump stage are connected in series between the supply voltage and the load capacitor, and
wherein another first capacitor of the first charge pump stage and another second capacitor of the second charge pump stage each couple the supply voltage to ground in parallel.
17 . The method of claim 15 , further comprising:
connecting in series in the first branch, a first n-channel field effect transistor, the first capacitors and an additional first n-channel field effect transistor in between an input voltage node and ground.
18 . The method of claim 17 , further comprising:
cross-coupling the first n-channel field transistors and controlling the additional first n-channel field effect transistors by a clock signal and an inverted clock signal, respectively.