Imaging element and imaging device
Provided is an imaging element according to an embodiment of the present disclosure that includes an imaging section in which a plurality of pixels individually including a photoelectric conversion element is arranged in a matrix, a convolution circuit that performs convolution processing on a plurality of pixel signals, which are analog signals each output from the plurality of pixels, on a basis of a convolution coefficient, and a pooling circuit that performs pooling processing on the plurality of pixel signals that has been subjected to the convolution processing.
1 . An imaging element, comprising:
an imaging section in which a first plurality of pixels is arranged in a matrix, wherein each pixel of the first plurality of pixels includes a photoelectric conversion element;
a convolution circuit configured to execute convolution processing on a plurality of pixel signals based on a convolution coefficient, wherein
the plurality of pixel signals are analog signals,
each of the plurality of pixel signals is output from the first plurality of pixels, and
the convolution circuit includes:
a horizontal scanning circuit configured to select, based on the convolution coefficient, a second plurality of pixels of the first plurality of pixels, wherein the plurality of pixel signals is output from the selected second plurality of pixels; and
an addition circuit configured to add, based on the convolution coefficient, each pixel signal of the plurality of pixel signals output from the selected second plurality of pixels; and
a pooling circuit configured to execute pooling processing on the plurality of pixel signals subjected to the convolution processing.
2 . The imaging element according to claim 1 , further comprising
a fully integrated processing section that performs fully integrated processing on the plurality of pixel signals that has been subjected to the pooling processing.
3 . The imaging element according to claim 1 , wherein the addition circuit includes a multiplexer for setting the convolution coefficient and a plurality of capacitors.
4 . The imaging element according to claim 1 , wherein the addition circuit includes a plurality of amplifiers configured to set the convolution coefficient.
5 . The imaging element according to claim 1 , further comprising a storage section configured to store the convolution coefficient.
6 . The imaging element according to claim 1 , further comprising a control section configured to control the convolution circuit and the pooling circuit based on the convolution coefficient.
7 . The imaging element according to claim 6 , wherein the control section is further configured to restrict or permit the convolution processing and the pooling processing based on an input signal input to the control section.
8 . The imaging element according to claim 1 ,
wherein the convolution coefficient is a convolution filter, and
the convolution circuit is further configured to:
shift the convolution filter in a specific movement amount, and
execute the convolution processing based on the shift of the convolution filter.
9 . The imaging element according to claim 1 , wherein the convolution coefficient is a convolution filter including zero.
10 . An imaging device, comprising:
an imaging element; and
an optical system configured to form an image of light on a light receiving surface of the imaging element, wherein the imaging element includes:
an imaging section in which a first plurality of pixels is arranged in a matrix, wherein each pixel of the first plurality of pixels includes a photoelectric conversion element;
a convolution circuit configured to execute convolution processing on a plurality of pixel signals based on a convolution coefficient, wherein
the plurality of pixel signals are analog signals,
each of the plurality of pixel signals is output from the first plurality of pixels, and
the convolution circuit includes:
a horizontal scanning circuit configured to select, based on the convolution coefficient, a second plurality of pixels of the first plurality of pixels, wherein the plurality of pixel signals is output from the selected second plurality of pixels; and
an addition circuit configured to add, based on the convolution coefficient, each pixel signal of the plurality of pixel signals output from the selected second plurality of pixels; and
a pooling circuit configured to execute pooling processing on the plurality of pixel signals subjected to the convolution processing.