IP Library Granted Patent US 12,635,489
Granted Patent B2
US 12,635,489 · App. 18/353,697 · Granted May 19, 2026

High voltage semiconductor device and method of manufacturing same

Inventor: Jong Won Sun (Icheon-si, KR)
Assignee: DB HiTek Co., Ltd.
H10W10/17H10D84/00H10W10/0145H10W10/021H10W10/20
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Quick Facts
Patent No.
US 12,635,489
App. No.
18/353,697
Granted
May 19, 2026
Kind
B2
Abstract

Proposed is a high voltage semiconductor device and a method of manufacturing the same and, more particularly, a high voltage semiconductor device and a method of manufacturing the same, which allow the upper end of an air gap or void formed in a DTI region to be positioned relatively deep in a substrate by forming a wide region with a relatively wide lateral width on the upper part of the DTI region, thereby preventing external exposure of the air gap in a subsequent process and preventing foreign substances such as tungsten from remaining on the upper side of the DTI region accordingly.

Claims (30)

1 . A high voltage semiconductor device, comprising:

a substrate;

a gate electrode disposed on the substrate;

a source region disposed on a surface of the substrate and a drain region spaced apart from the source region;

a DTI region extending to a predetermined depth from the surface of the substrate and including an insulating material; and

an STI region surrounding one side of the DTI region in the substrate,

wherein the DTI region comprises:

a wide region positioned at an upper side of the DTI region;

a narrow region extending from a bottom of the wide region to a predetermined depth of the substrate and having a lateral width less than a lateral width of the wide region; and

an air gap disposed in the DTI region,

wherein the wide region includes an inclined surface at a sidewall of a lower portion thereof connecting to an upper portion of the narrow region, such that a lateral width of the DTI region at the inclined surface gradually narrows in a downward direction,

wherein the lateral width of the DTI region at the inclined surface narrows more sharply in the downward direction than both a lateral width of the DTI region at a remaining part of the wide region and the lateral width of the DTI region at the narrow region, and

wherein an upper end of the air gap is positioned deeper than a bottom of the STI region.

2 . The high voltage semiconductor device of claim 1 , wherein the inclined surface has a cross-sectional shape of a curved sidewall.

3 . The high voltage semiconductor device of claim 1 , wherein the wide region is formed by etching an upper region of a trench after forming the trench for the narrow region.

4 . The high voltage semiconductor device of claim 1 , wherein a lateral width of the bottom of the wide region is substantially equal to a lateral width of an uppermost part of the narrow region.

5 . The high voltage semiconductor device of claim 1 , wherein the narrow region has a scallop structure on at least one side wall thereof.

6 . The high voltage semiconductor device of claim 1 ,

wherein a maximum lateral width of the wide region is greater than a maximum lateral width of the narrow region.

7 . The high voltage semiconductor device of claim 6 , wherein the wide region has a substantially same lateral width as a lateral width of the narrow region at a boundary with the narrow region.

8 . The high voltage semiconductor device of claim 6 , further comprising:

a body region surrounding the source region in the substrate;

a deep well region surrounding a first well region in the substrate;

the first well region surrounding the drain region in the deep well region;

a buried layer disposed beneath the deep well region in the substrate; and

a high-voltage well region connected to both the buried layer and the deep well region in the substrate.

9 . The high voltage semiconductor device of claim 1 , wherein the narrow region has a constant width as it extends in the downward direction.

10 . The high voltage semiconductor device of claim 1 , wherein the inclined surface has a cross-sectional shape of a straight sidewall as it extends in the downward direction.

11 . The high voltage semiconductor device of claim 1 , wherein the inclined surface has a cross-sectional shape including both a curved portion and a straight portion.

12 . The high voltage semiconductor device of claim 1 , wherein a bottom of the inclined surface is positioned deeper than the bottom of the STI region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2023
From: SUN, JONG WON
To: DB HITEK CO., LTD.
Reel/Frame 064294/0504 →
Priority Claims (1)
KR 10-2023-0068165 · May 26, 2023 · national
Continuity (1)
Related Publication 20240395599A1 · Nov 28, 2024
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