Gate driver and display apparatus including same
Provided is a gate driver including a plurality of stages, wherein each stage includes an output unit including a pull-up transistor and a pull-down transistor, and a second node controller configured to control a voltage of a second control node to which a gate of the pull-up transistor is connected, wherein the second node controller includes a first control transistor connected between the first clock terminal and the second control node and including a gate connected to the first control node, and a second control transistor including a gate connected to the gate of the first control transistor and configured to control a short circuit between the first clock terminal and a second clock terminal.
1 . A gate driver including a plurality of stages, wherein each of the plurality of stages comprises:
a first transistor connected between a first input terminal to which a start signal is applied and a first control node;
a second transistor connected between a second input terminal to which a first signal is applied and an output terminal, and including a gate connected to a second control node;
a third transistor connected between the output terminal and a third input terminal to which a second signal is applied, and including a gate connected to the first control node;
a fourth transistor connected between the second input terminal and the second control node,
a fifth transistor connected between the second control node and a fourth input terminal to which a third signal is applied; and
a sixth transistor connected between the second input terminal and a gate of the fifth transistor,
wherein the fourth transistor is configured to control the second control node based on a voltage of the first control node, and
wherein the third signal is a first clock signal alternating a first voltage for turning on the second transistor and a second voltage for turning off the second transistor.
2 . The gate driver of claim 1 , wherein a gate of the fourth transistor is connected to the first control node.
3 . The gate driver of claim 1 , wherein a second clock signal is applied to a gate of the first transistor, and
wherein the first clock signal and the second clock signal have a same waveform and have a phase difference.
4 . The gate driver of claim 3 , wherein the first signal is the first clock signal.
5 . The gate driver of claim 3 , wherein the second signal is the second voltage.
6 . The gate driver of claim 5 , further comprising a first capacitor connected between the second input terminal and the second control node; and
a seventh transistor connected between the first transistor and the first control node.
7 . The gate driver of claim 6 , wherein the second voltage is applied to a gate of the seventh transistor.
8 . The gate driver of claim 6 , wherein the start signal is an external signal or an output signal output from an output terminal of a previous stage.
9 . The gate driver of claim 6 , further comprising:
an eighth transistor connected between a first node and the fourth input terminal, and including a gate connected to the first control node; and
a second capacitor connected between the first control node and the first node.
10 . The gate driver of claim 1 ,
wherein, when the sixth transistor is turned on, the fifth transistor is turned off.
11 . The gate driver of claim 9 , further comprising:
a ninth transistor connected between a second node and the third input terminal, and including a gate connected to the second input terminal;
a tenth transistor connected between the second node and a third node, and including a gate connected to the third input terminal;
an eleventh transistor connected between a fourth node and the second control node, and including a gate connected to the fourth input terminal; and
a third capacitor connected between the third node and the fourth node.
12 . The gate driver of claim 11 , further comprising a twelfth transistor connected between the fifth transistor and the fourth input terminal, and including a gate connected to the third node.
13 . An electronic apparatus comprising:
a controller outputting control signals; and
a gate driver configured to output gate signals to a plurality of pixels in response to the control signals,
wherein the gate driver includes a plurality of stages, and
each of the plurality of stages includes:
a first transistor connected between a first input terminal to which a start signal is applied, and a first control node;
a second transistor connected between a second input terminal to which a first signal is applied, and an output terminal, and including a gate connected to a second control node;
a third transistor connected between the output terminal and a third input terminal to which a second signal is applied, and including a gate connected to the first control node;
a fourth transistor connected between the second input terminal and the second control node;
a fifth transistor connected between the second control node and a fourth input terminal to which a third signal is applied; and
a sixth transistor connected between the second input terminal and a gate of the fifth transistor,
wherein the fourth transistor is configured to control the second control node based on a voltage of the first control node, and
wherein the third signal is a first clock signal alternating a first voltage for turning on the second transistor and a second voltage for turning off the second transistor.
14 . The electronic apparatus of claim 13 , wherein a gate of the fourth transistor is connected to the first control node.
15 . The electronic apparatus of claim 13 , wherein a second clock signal is applied to a gate of the first transistor, and
wherein the first clock signal and the second clock signal have a same waveform and have a phase difference.
16 . The electronic apparatus of claim 15 , wherein the first signal is the first clock signal.
17 . The electronic apparatus of claim 13 , wherein the second signal is the second voltage.
18 . The electronic apparatus of claim 17 , further comprising a first capacitor connected between the second input terminal and the second control node; and
a seventh transistor connected between the first transistor and the first control node,
wherein the second voltage is applied to a gate of the seventh transistor.
19 . The electronic apparatus of claim 18 , further comprising:
an eighth transistor connected between a first node and the fourth input terminal, and including a gate connected to the first control node;
a second capacitor connected between the first control node and the first node;
a ninth transistor connected between a second node and the third input terminal, and including a gate connected to the second input terminal;
a tenth transistor connected between the second node and a third node, and including a gate connected to the third input terminal;
an eleventh transistor connected between a fourth node and the second control node, and including a gate connected to the fourth input terminal; and
a third capacitor connected between the third node and the fourth node.
20 . The electronic apparatus of claim 13 , wherein, when the sixth transistor is turned on, the fifth transistor is turned off.