Apparatus to reduce polarization targets or improve memory density for non-linear polar material based memory
Described herein is a method and apparatus to reduce electric displacement and polarization target for a memory bit-cell. In at least one embodiment, electric displacement and polarization target for non-linear polar material based memory bit-cells is reduced by re-architecting the memory. In at least one embodiment, memory is architected to reduce electric displacement and polarization target by reducing capacitance on sense line or bit-line for bit-cell being accessed or written to. In at least one embodiment, memory arrays are actively split into two or more sub-arrays and routing capacitance is reduced, which in turn reduces capacitance on sense line or bit-line.
1 . An apparatus comprising:
a first set of plurality of memory bit-cells coupled to a first bit-line;
a second set of plurality of memory bit-cells coupled to a second bit-line, wherein an individual bit-cell of the first set of plurality of memory bit-cells and the second set of plurality of memory bit-cells comprises a transistor and a capacitor coupled to the transistor, and wherein the transistor comprises non-linear polar material;
a third bit-line;
a first isolation circuitry to selectively couple or decouple the first bit-line to the third bit-line;
a second isolation circuitry to selectively couple or decouple the second bit-line to the third bit-line; and
a gain circuitry coupled to the third bit-line via one or more devices, wherein the gain circuitry comprises a gain transistor and a series transistor coupled in series with the gain transistor, and wherein a size of the gain transistor is larger than a size of the series transistor.
2 . The apparatus of claim 1 , wherein the gain transistor having a gate terminal coupled to the third bit-line via the one or more devices; and wherein the series transistor is coupled in series with the gain transistor, wherein the series transistor is controllable by a read word-line, and wherein the series transistor is coupled to a sense line.
3 . The apparatus of claim 2 , wherein the gain transistor is larger in size than the series transistor.
4 . The apparatus of claim 2 , wherein the gain transistor is coupled to a reference voltage.
5 . The apparatus of claim 1 comprises a sense amplifier to sense a voltage on the third bit-line.
6 . The apparatus of claim 1 comprises a first pre-charge circuitry coupled to the first bit-line, wherein the first pre-charge circuitry is to pre-charge the first bit-line after the first isolation circuitry decouples the first bit-line from the third bit-line.
7 . The apparatus of claim 1 comprises a second pre-charge circuitry coupled to the second bit-line, wherein the second pre-charge circuitry is to pre-charge the second bit-line after the second isolation circuitry decouples the second bit-line from the third bit-line.
8 . The apparatus of claim 1 comprises a logic circuitry to generate a first control for the first isolation circuitry to selectively couple or decouple the first bit-line to the third bit-line.
9 . The apparatus of claim 1 comprises a logic circuitry to generate a second control for the second isolation circuitry to selectively couple or decouple the second bit-line to the third bit-line.
10 . The apparatus of claim 1 , wherein the non-linear polar material is one of a ferroelectric, paraelectric, or non-linear dielectric material.
11 . The apparatus of claim 1 , wherein the non-linear polar material is doped one or more elements of a 3d, 4d, 5d, 6d, 4f, and 5f series of a periodic table.
12 . The apparatus of claim 1 , wherein the non-linear polar material includes one of:
a perovskite material which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , or NaTaO 3 ;
bismuth ferrite (BFO);
barium titanate (BTO);
BFO doped with one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn;
BTO doped with one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn;
LBFO doped with Mn;
lead zirconium titanate (PZT) or PZT with a first doping material, wherein the first doping material is one of La, Nb, Mn, or 5d series elements;
bismuth ferrite (BFO) with a second doping material, wherein the second doping material is one of lanthanum, elements from lanthanide series of a periodic table, or elements of a 3d, 4d, 5d, 6d, 4f, and 5f series of the periodic table;
a relaxor ferroelectric material which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a first hexagonal ferroelectric which includes one of: YMnO 3 or LuFeO 3 ;
a second hexagonal ferroelectric of a type h-RMnO 3 , wherein R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides;
hafnium oxides in a form of Hf( 1-x ) E x O y , where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, where ‘x’ and ‘y’ are first and second fractions, respectively;
Al( 1-x )Sc( x )N, Ga( 1-x )Sc( x )N, Al( 1-x )Y( x )N or Al( 1-x-y )Mg( x )Nb( y )N, where ‘x’ and ‘y’ are third and fourth fractions, respectively;
y doped HfO 2 , where ‘y’ includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y; or
niobate type compounds LiNbO 3 , LiTaO 3 , lithium iron tantalum oxyfluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate;
an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, wherein ‘n’ is between 1 and 100, or a paraelectric material that comprises SrTiO 3 , Ba( x )Sr( y )TiO 3 , HfZrO 2 , Hf—Si—O, La-substituted PbTiO 3 , or a PMN-PT based relaxor ferroelectric, where ‘x’ and ‘y’ are fifth and sixth fractions, respectively; or
a paraelectric material that comprises SrTiO 3 , Ba( x )Sr( y )TiO 3 , HfZrO 2 , Hf—Si—O, or a PMN-PT based relaxor ferroelectric, where ‘x’ and ‘y’ are seventh and eighth fractions, respectively.
13 . An apparatus comprising:
one or more circuitries to split a memory into two or more memory sub-arrays based at least in part on a polarization target of capacitors of the memory, wherein the capacitors include non-linear polar material; and a gain circuitry coupled to a global bit-line via one or more devices, wherein the gain circuitry comprises a gain transistor and a series transistor coupled in series with the gain transistor, and wherein a size of the gain transistor is larger than a size of the series transistor.
14 . The apparatus of claim 13 , wherein the one or more circuitries include a transistor to couple or decouple a local bit-line, of a memory sub-array of the two or more memory sub-arrays, to global bit-line.
15 . The apparatus of claim 14 , wherein the global bit-line is coupled to a sense amplifier.
16 . The apparatus of claim 13 , wherein the gain transistor having a gate terminal coupled to the global bit-line via the one or more devices; and wherein the series transistor coupled in series with the gain transistor, wherein the series transistor is controllable by a read word-line, and wherein the series transistor is coupled to a sense line.
17 . A system comprising:
a processor circuitry to execute one or more instructions;
a memory coupled to the processor circuitry;
a communication interface to allow the processor circuitry to communicate with another device, wherein the memory comprises:
a first set of plurality of memory bit-cells coupled to a first bit-line;
a second set of plurality of memory bit-cells coupled to a second bit-line, wherein an individual bit-cell of the first set of plurality of memory bit-cells and the second set of plurality of memory bit-cells comprises a transistor and a capacitor coupled to the transistor, and wherein the transistor comprises non-liner polar material;
a third bit-line;
a first isolation circuitry to selectively couple or decouple the first bit-line to the third bit-line; and
a second isolation circuitry to selectively couple or decouple the second bit-line to the third bit-line; and
a gain circuitry coupled to the third bit-line via one or more devices, wherein the gain circuitry comprises a gain transistor and a series transistor coupled in series with the gain transistor, wherein a size of the gain transistor is larger than a size of the series transistor, wherein the gain transistor is coupled to a reference voltage, and wherein the series transistor is controllable by a read word-line.