IP Library Granted Patent US 12,640,197
Granted Patent B2
US 12,640,197 · App. 18/385,281 · Granted May 26, 2026

Determination of a bias voltage by applying a series of increasing currents to bit line of memory cell in a neural network

Inventor: Hieu Van Tran (San Jose, CA)
Assignee: Silicon Storage Technology, Inc.
G11C11/54G06N3/063G11C16/0425G11C16/10G11C16/24G11C16/26H10B41/30
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Quick Facts
Patent No.
US 12,640,197
App. No.
18/385,281
Granted
May 26, 2026
Kind
B2
Abstract

A first example comprises programming a memory cell to store a value; applying a series of currents of increasing size to a bit line of the memory cell; and measuring a voltage of a control gate terminal of the memory cell to determine a bias. A second example comprises programming a memory cell to store a value; applying a predetermined current to a bit line of the memory cell; and measuring a voltage of a control gate terminal of the memory cell to determine a bias.

Claims (16)

1 . A method comprising:

programming a memory cell to store a value;

applying a series of currents of increasing size to a bit line of the memory cell; and

when a voltage of the bit line exceeds a reference voltage, measuring a voltage of a control gate terminal of the memory cell to determine a bias.

2 . The method of claim 1 , comprising:

storing the bias.

3 . The method of claim 2 , comprising:

applying the bias to one or more memory cells in an array of memory cells during an operation on the one or more memory cells.

4 . The method of claim 3 , wherein the array is an analog neural memory array.

5 . The method of claim 2 , comprising:

performing the programming, applying, measuring, and storing steps for a plurality of different operating temperatures of the memory cell.

6 . A system comprising:

a circuit to program a memory cell to store a value; and

a circuit to apply a series of currents of increasing size to a bit line of the memory cell and to measure a voltage of a control gate terminal of the memory cell to determine a bias when a voltage of the bit line exceeds a reference voltage.

7 . The system of claim 6 , comprising:

a lookup table to store the bias.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2025
From: TRAN, HIEU VAN
To: SILICON STORAGE TECHNOLOGY, INC.
Reel/Frame 070594/0037 →
Continuity (3)
Division 17585452 · Jan 26, 2022
Provisional Application 63279028 · Nov 12, 2021
Related Publication 20240062813A1 · Feb 22, 2024
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