Bit counting circuits and memory devices including the same
A nonvolatile memory device includes a control logic configured to generate a clock signal and a page buffer selection signal including information about a ratio of a number of page buffers on which a fail bit counting operation is performed to a total number of the plurality of page buffers, a fail bit counting circuit configured to select one or more page buffers from among the plurality of page buffers, repeat the fail bit counting operation on the selected one or more page buffers, and output a value of a number of fail bits with respect to the page buffers on which the fail bit counting operation is performed, and a predictor configured to generate a prediction value with respect to a total number of fail bits with respect to the plurality of page buffers.
1 . A nonvolatile memory device comprising:
a memory cell array including a plurality of memory cells;
a plurality of page buffers connected to the memory cell array through bit lines;
a control logic configured to generate a clock signal and a page buffer selection signal, the page buffer selection signal including information about a ratio of a number of page buffers on which a fail bit counting operation is performed to a total number of the plurality of page buffers;
a fail bit counting circuit configured to:
select, based on the clock signal and the page buffer selection signal, one or more page buffers from among the plurality of page buffers,
repeat, based on a shift register, the fail bit counting operation on the selected one or more page buffers, and
output a value of a number of fail bits with respect to the selected one or more page buffers on which the fail bit counting operation is performed based on the repetition; and
a predictor configured to generate, based on the ratio of the number of page buffers on which the fail bit counting operation is performed to the total number of the plurality of page buffers and based on the number of fail bits with respect to the selected one or more page buffers on which the fail bit counting operation is performed, a prediction value with respect to a total number of fail bits with respect to the plurality of page buffers.
2 . The nonvolatile memory device of claim 1 , wherein the fail bit counting circuit includes at least one of a page buffer selector, a fail bit counter, and the shift register.
3 . The nonvolatile memory device of claim 2 , wherein the page buffer selector is configured to:
receive the page buffer selection signal and, in response to the page buffer selection signal, select the one or more page buffers from among the plurality of page buffers; and
output, from each of the selected one or more page buffers, data to the shift register.
4 . The nonvolatile memory device of claim 3 , wherein the shift register includes one or more D flip-flops and one or more multiplexers,
wherein the shift register is configured to receive the data from the page buffer selector, and when the data is a pass bit, pass the one or more D flip-flops through the one or more multiplexers, and when the data is a fail bit, receive the clock signal from the control logic, and
wherein the shift register is further configured to generate, from the data, a scan output signal by using the clock signal, the one or more D flip-flops, and the one or more multiplexers,
wherein a number of rising edges of the clock signal during a section in which the scan output signal has a logic high level is equal to the number of fail bits.
5 . The nonvolatile memory device of claim 4 , wherein the fail bit counter is configured to receive the scan output signal from the shift register and, based on the scan output signal, output the value of the number of fail bits with respect to the selected one or more page buffers.
6 . The nonvolatile memory device of claim 5 , wherein the predictor is configured to receive the page buffer selection signal from the control logic and the value of the number of fail bits with respect to the selected one or more page buffers from the fail bit counter.
7 . The nonvolatile memory device of claim 1 , wherein the predictor is configured to, during a first clock signal section, generate the prediction value, when the fail bit counting operation is performed on only some of the plurality of page buffers based on the repetition of the fail bit counting operation on the selected one or more page buffers.
8 . The nonvolatile memory device of claim 7 , wherein the predictor is further configured to refrain from generation, during the first clock signal section, of the prediction value when the fail bit counting operation is performed on all of the plurality of page buffers based on the repetition of the fail bit counting operation on the selected one or more page buffers.
9 . A nonvolatile memory device comprising:
a memory cell array including a plurality of memory cells;
a plurality of page buffers connected to the memory cell array through bit lines;
a control logic configured to generate a clock signal;
a page buffer selection signal control circuit configured to generate a page buffer selection signal including information about a ratio of a number of page buffers on which a fail bit counting operation is performed to a total number of the plurality of page buffers;
a fail bit counting circuit configured to: select, based on the clock signal and the page buffer selection signal, one or more page buffers from among the plurality of page buffers, repeat, based on a shift register, the fail bit counting operation on the selected one or more page buffers, and output a value of a number of fail bits with respect to the selected one or more page buffers on which the fail bit counting operation is performed based on the repetition; and
a predictor configured to generate, based on the ratio of the number of page buffers on which the fail bit counting operation is performed to the total number of the plurality of page buffers and the number of fail bits with respect to the selected one or more page buffers on which the fail bit counting operation is performed, a prediction value with respect to a total number of fail bits with respect to the plurality of page buffers.
10 . An operating method of a nonvolatile memory device including a plurality of page buffers, the operating method comprising:
selecting one or more page buffers from among the plurality of page buffers and repeating a fail bit counting operation on the selected one or more page buffers based on a shift register;
generating a value of a number of fail bits with respect to the selected one or more page buffers on which the fail bit counting operation is performed based on the repetition; and
generating, based on a ratio of a number of the selected one or more page buffers on which the fail bit counting operation is performed to a total number of the plurality of page buffers and the number of fail bits with respect to the selected one or more page buffers on which the fail bit counting operation is performed, a prediction value with respect to a total number of fail bits with respect to the plurality of page buffers.
11 . The operating method of claim 10 , wherein the generating of the prediction value includes, during a first clock signal section, generating the prediction value when the fail bit counting operation is performed on only some of the plurality of page buffers based on the repetition of the fail bit counting operation on the selected one or more page buffers.
12 . The operating method of claim 11 , further comprising, during the first clock signal section, refraining from generating the prediction value when the fail bit counting operation is performed on all of the plurality of page buffers based on the repetition of the fail bit counting operation on the selected one or more page buffers.
13 . The operating method of claim 10 , wherein the generating of the prediction value includes, during a first clock signal section, generating the prediction value when the fail bit counting operation is performed on only some of the plurality of page buffers based on the repetition of the fail bit counting operation on the selected one or more page buffers, and based on a number of counted fail bits being greater than or equal to a predetermined number.
14 . The operating method of claim 13 , further comprising, during the first clock signal section, refraining from generating the prediction value when the fail bit counting operation is performed on only some of the plurality of page buffers based on the repetition of the fail bit counting operation on the selected one or more page buffers, and based on the number of counted fail bits being less than the predetermined number.
15 . The operating method of claim 13 , further comprising, during the first clock signal section, refraining from generating the prediction value when the fail bit counting operation is performed on all of the plurality of page buffers based on the repetition of the fail bit counting operation on the selected one or more page buffers.
16 . The operating method of claim 10 , wherein the shift register includes a D flip-flop and a multiplexer through which the D flip-flop is passed with respect to a pass bit.
17 . The operating method of claim 10 , wherein, with respect to the fail bit counting operation on the selected one or more page buffers based on the shift register, a number of rising edges of a clock signal during a section in which a scan output signal has a logic high level is equal to the number of fail bits.
18 . The operating method of claim 10 , wherein the selecting of the one or more page buffers from among the plurality of page buffers includes dividing the plurality of page buffers into a predetermined number of groups and selecting at least one page buffer for each group.
19 . The operating method of claim 18 , wherein the ratio of the number of the selected one or more page buffers on which the fail bit counting operation is performed to the total number of the plurality of page buffers corresponds to a ratio of the at least one page buffer selected for each group to total page buffers of each group.
20 . The operating method of claim 10 , further comprising applying at least one of a program voltage, an erase voltage, and a read voltage to a memory cell array of the nonvolatile memory device based on at least one of the value of the number of fail bits and the prediction value.