Host-to-device interface circuitry testing
Some implementations provide systems methods and devices for integrated circuit self-test. The integrated circuit includes interface circuitry configured to read test data and to write the test data into memory of the integrated circuit. The integrated circuit also includes test circuitry configured to test the interface circuitry based on the test data written into memory of the integrated circuit. Some implementations provide an integrated circuit configured for storing and reading data. The integrated circuit includes circuitry configured to write or read a first portion of data to or from a first memory via BIST circuitry of the first memory until a first BIST counter saturates. The integrated circuit also includes circuitry configured to write or read a second portion of the data to or from a second memory via BIST circuitry of the second memory until a second BIST counter saturates.
1 . An integrated circuit configured for self-test, comprising:
interface circuitry configured to communicate test data between a device outside of the integrated circuit and the integrated circuit;
storage circuitry configured to store the test data in memory of the integrated circuit; and
test circuitry configured to place the integrated circuit in a self-test mode, wherein the self-test mode:
isolates circuitry other than the interface circuitry from testing and prevents communication with the device outside of the integrated circuit, and
tests the interface circuitry using the test data retrieved from the memory of the integrated circuit by applying the test data as input to the interface circuitry and comparing output produced by the interface circuitry with expected output data stored in the memory.
2 . The integrated circuit of claim 1 , wherein the interface circuitry is configured to receive the test data from an external storage device.
3 . The integrated circuit of claim 1 , wherein the memory of the integrated circuit comprises a plurality of memories, wherein the plurality of memories are on a same die as the integrated circuit, are within a same package as the integrated circuit, or are both on a same die as the integrated circuit and within a same package as the integrated circuit.
4 . The integrated circuit of claim 1 , wherein the memory of the integrated circuit comprises a memory pool.
5 . The integrated circuit of claim 1 , wherein the memory of the integrated circuit comprises a plurality of memories, wherein the plurality of memories are configured to be accessed serially, are configured to be written to and read from via built-in self-test (BIST) circuitry, or are both configured to be accessed serially and configured to be written to and read from via BIST circuitry.
6 . The integrated circuit of claim 1 , wherein the memory comprises a first memory and a second memory; and wherein the interface circuitry is configured to store a first portion of the test data in the first memory on the integrated circuit until the first portion of the test data has been entirely stored in the first memory, and, after the first portion of the test data has been entirely stored in the first memory, to store a second portion of the test data in the second memory on the integrated circuit.
7 . The integrated circuit of claim 1 , wherein the memory comprises a first memory and a second memory; and wherein the test circuitry is configured to receive a first portion of the test data from the first memory on the integrated circuit until the first portion of the test data has been entirely received from the first memory, and, after the first portion of the test data has been entirely received, receiving a second portion of the test data from the second memory on the integrated circuit.
8 . A method for testing an integrated circuit, the method comprising:
storing test data in memory of the integrated circuit over interface circuitry configured to communicate test data between a device outside of the integrated circuit and the integrated circuit; and
entering a self-test mode, wherein the self-test mode:
isolates circuitry other than the interface circuitry from testing and prevents communication with the device outside of the integrated circuit, and
tests the interface circuitry using the test data retrieved from the memory of the integrated circuit by applying the test data as input to the interface circuitry and comparing output produced by the interface circuitry with expected output data stored in the memory.
9 . The method of claim 8 , wherein the test data is stored in the memory on the integrated circuit over the interface circuitry of the integrated circuit from an external storage device.
10 . The method of claim 8 , wherein the memory of the integrated circuit comprises a plurality of memories, wherein the plurality of memories are on a same die as the integrated circuit, are within a same package as the integrated circuit, or are both on a same die as the integrated circuit and within a same package as the integrated circuit.
11 . The method of claim 8 , wherein the memory of the integrated circuit comprises a memory pool.
12 . The method of claim 8 , wherein the memory of the integrated circuit comprises a plurality of memories, wherein the plurality of memories are configured to be accessed serially, are configured to be written to and read from via built-in self-test (BIST) circuitry, or are both configured to be accessed serially and configured to be written to and read from via BIST circuitry.
13 . The method of claim 8 , wherein storing the test data in the memory on the integrated circuit over the interface circuitry comprises storing a first portion of the test data in a first memory on the integrated circuit until the first portion of the test data has been entirely stored in the first memory, and, after the first portion of the test data has been entirely stored in the first memory, storing a second portion of the test data in a second memory on the integrated circuit until the second portion of the test data has been entirely stored in the second memory.
14 . The method of claim 8 , wherein testing the interface circuitry based on the test data comprises receiving a first portion of the test data from a first memory on the integrated circuit until the first portion of the test data has been entirely received from the first memory, and, after the first portion of the test data has been entirely received, receiving a second portion of the test data from a second memory on the integrated circuit until the second portion of the test data has been entirely received from the second memory.
15 . The method of claim 8 , wherein testing the interface circuitry based on the test data written into the memory of the integrated circuit comprises receiving the test data from the memory of the integrated circuit, applying the test data to the interface circuitry to generate test output data, and comparing the test output data to expected output data stored in the memory while communication with the device outside of the integrated circuit is prevented.
16 . An integrated circuit configured for storing data, comprising:
interface circuitry configured to communicate data between a device outside of the integrated circuit and the integrated circuit and storage circuitry configured to store a first portion of the data in a first memory via built-in self-test (BIST) circuitry of the first memory while incrementing a first BIST counter of the first memory until the first BIST counter reaches a terminal saturation count and asserts a hardware trigger;
circuitry configured to, responsive to the asserted hardware trigger, store a second portion of the data in a second memory via BIST circuitry of the second memory while incrementing a second BIST counter of the second memory until the second BIST counter reaches a terminal saturation count; and
test circuitry configured to place the integrated circuit in a self-test mode, wherein the self-test mode:
isolates circuitry other than the interface circuitry from testing, and
tests the interface circuitry based on the first portion and the second portion.
17 . The integrated circuit of claim 16 , further comprising circuitry configured to trigger storing of the second portion of the data in the second memory based on saturation of the first BIST counter.
18 . The integrated circuit of claim 16 , wherein the first memory and the second memory are comprised of the integrated circuit or an integrated circuit die, and the integrated circuit comprises circuitry configured to receive the data from a memory device that is external to the integrated circuit or to the integrated circuit die.
19 . The integrated circuit of claim 16 , wherein the first memory and the second memory are comprised of an integrated circuit package, and the integrated circuit comprises circuitry configured to receive the data from a memory device that is external to the integrated circuit package.
20 . The integrated circuit of claim 1 , wherein the self-test mode prevents communication with the device outside of the integrated circuit and configures the interface circuitry to be exercised exclusively using the test data and expected output data retrieved from the memory of the integrated circuit.