Signal skew correction in integrated circuit memory devices
Technologies for signal skew correction in integrated circuit memory devices are described. An integrated circuit memory device includes a first interface to receive command/address (CA) signals and a clock signal, a data interface, and a mode register. During a CA bus loopback mode, the first interface receives a pattern of CA signals and the clock signal and the data interface outputs the pattern of CA signals. During the CA bus loopback mode, the mode register can be programmed with a value representative of a timing offset between the clock signal and a sampling point for the first interface.
1 . An integrated circuit memory device comprising:
a first interface configured to receive command/address (CA) signals and a clock signal, the first interface having a receiver for each of the CA signals;
a data interface, wherein the first interface, in a CA bus loopback mode, is configured to receive a pattern of CA signals and the data interface, in the CA bus loopback mode, is configured to output the received pattern of CA signals;
a mode register configured to store values representative of a timing offset between the clock signal and a sampling point for the first interface, wherein the values include a first value and a second value;
a first delay element controlled by the first value stored in the mode register to delay a clock edge by a first programmable delay; and
a plurality of delay elements, wherein each delay element is controlled by the second value stored in the mode register to delay a sampling point for each receiver of the first interface, for each corresponding CA signal, by a second programmable delay.
2 . The integrated circuit memory device of claim 1 , further comprising:
a programmable delay line coupled between a clock terminal and a clock buffer, the programmable delay line comprising the first delay element and a second delay element; and
a delay locked loop (DLL) circuit, wherein the DLL circuit is configured to control a programmable delay of the programmable delay line using the first delay element and the second delay element.
3 . The integrated circuit memory device of claim 1 , further comprising:
a first plurality of delay elements, wherein the first plurality of delay elements is controlled by a first set of values stored in the mode register to delay a receiver of each clock line corresponding to each CA bit by a first set of programmable delays; and
a second plurality of delay elements, wherein the second plurality of delay elements is controlled by a second set of values stored in the mode register to delay a receiver of each CA bit by a second set of programmable delays.
4 . The integrated circuit memory device of claim 1 , further comprising:
a first CA line of a plurality of CA lines;
a clock (CK) line;
the first delay element on the CK line, wherein the first delay element is controlled by the first value stored in the mode register to delay a clock signal on the CK line by the first programmable delay; and
a second delay element, of the plurality of delay elements, on the first CA line, wherein the second delay element is controlled by the second value stored in the mode register to delay a CA signal on the first CA line by the second programmable delay.
5 . The integrated circuit memory device of claim 4 , further comprising:
a chip select (CS) line; and
a third delay element on the CS line, wherein the third delay element is controlled by the second value stored in the mode register to delay a CS signal on the CS line by the second programmable delay.
6 . The integrated circuit memory device of claim 4 , further comprising:
a second CA line of the plurality of CA lines; and
a fourth delay element on the second CA line, wherein the fourth delay element is controlled by the second value stored in the mode register to delay a second CA signal on the second CA line by the second programmable delay.
7 . The integrated circuit memory device of claim 4 , further comprising:
a second CA line of the plurality of CA lines; and
a fourth delay element on the second CA line, wherein the fourth delay element is controlled by a third value stored in the mode register to delay a second CA signal on the second CA line by a third programmable delay.